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VR4102 Datasheet(PDF) 333 Page - NEC |
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VR4102 Datasheet(HTML) 333 Page - NEC |
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333 / 701 page ![]() CHAPTER 15 PMU (POWER MANAGEMENT UNIT) 333 15.2.4 PMUCNT2REG (0x0B00 00A6) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name GPIO12MSK GPIO11MSK GPIO10MSK GPIO9MSK GPIO12TRG GPIO11TRG GPIO10TRG GPIO9TRG R/W R/W R/W R/W R/W R/W R/W R/W R/W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit D7 D6D5 D4D3D2 D1 D0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R/W R RR RRR R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D[15] GPIO12MSK GPIO[12] activation enable 1 : Enable 0 : Prohibit D[14] GPIO11MSK GPIO[11] activation enable 1 : Enable 0 : Prohibit D[13] GPIO10MSK GPIO[10] activation enable 1 : Enable 0 : Prohibit D[12] GPIO9MSK GPIO[9] activation enable 1 : Enable 0 : Prohibit D[11] GPIO12TRG GPIO[12] activation interrupt type 1 : Falling edge detection 0 : Rising edge detection D[10] GPIO11TRG GPIO[11] activation interrupt type 1 : Falling edge detection 0 : Rising edge detection D[9] GPIO10TRG GPIO[11] activation interrupt type 1 : Falling edge detection 0 : Rising edge detection D[8] GPIO9TRG GPIO[9] activation interrupt type 1 : Falling edge detection 0 : Rising edge detection D[7:0] Reserved Write 0 when writing. 0 is returned after a read. This register is used to specify the settings for activation via GPIO [12:9] interrupts. The GPIO activation interrupt is valid only when the CPU’s operation mode is Hibernate mode. |
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