VR4102 datasheet(331/701 Pages) NEC

331 / 701 page

CHAPTER 15 PMU (POWER MANAGEMENT UNIT)

331

(2/2)

Bit

Name

Function

D[6..3]

Reserved

Write 0 when writing. 0 is returned after a read.

D[2]

HALTIMERRST

HAL timer reset

1 : Reset

0 : Set

D[1]

Reserved

Write 1 when writing. 1 is returned after a read.

D[0]

Reserved

Write 0 when writing. 0 is returned after a read.

This register is used to set CPU shutdown and overall system management operations.

The HALTIMERRST bit must be reset within about four seconds of activation. Resetting of the HALTIMERRST

bit indicates that the VR4102 itself has been activated normally. If the HALTIMERRST bit is not reset within about

four seconds of activation, program execution is regarded as abnormal (possibly due to a runaway) and an

automatic shutdown is performed.

The GPIO[3..0]MSK bits are used to set enable/prohibit for activation from Hibernate mode when the

corresponding interrupt (GPIO[3..0]) occurs. The GPIO3MSK bit is set to 1 by RTCRST, and the other bits are

cleared to “0” (prohibit). Accordingly, the GPIO[2..0] cannot be used for activation immediately after an RTCRST

reset. The GPIO activation interrupt is valid only when the CPU’s operation mode is Hibernate mode.

VR4102 Datasheet(PDF) 331 Page - NEC