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VR4102 Datasheet(PDF) 328 Page - NEC |
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VR4102 Datasheet(HTML) 328 Page - NEC |
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328 / 701 page ![]() CHAPTER 15 PMU (POWER MANAGEMENT UNIT) 328 15.2.1 PMUINTREG (0x0B00 00A0) (1/2) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name GPIO3INTR GPIO2INTR GPIO1INTR GPIO0INTR Reserved DCDST RTCINTR BATTINH R/W R/W R/W R/W R/W R R R/W R/W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit D7 D6D5 D4D3D2 D1 D0 Name BATTLOCK CARDLOCK TIMOUTRST RTCRST RSTSW DMSRST BATTINTR POWERSW INTR R/W R/W R/W R/W R/W R/W R/W R/W R/W RTCRST 0 0 0 1 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D[15] GPIO3INTR GPIO[3] activation interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected D[14] GPIO2INTR GPIO[2] activation interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected D[13] GPIO1INTR GPIO[1] activation interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected D[12] GPIO0INTR GPIO[0] activation interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected D[11] Reserved Write 0 when writing. 0 is returned after a read. D[10] DCDST DCD# pin state. 1 : High 0 : Low D[9] RTCINTR RTC alarm interrupt detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected D[8] BATTINH Battery low detection during activation. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected |
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