VR4102 datasheet(327/701 Pages) NEC

327 / 701 page

CHAPTER 15 PMU (POWER MANAGEMENT UNIT)

327

(4) Hibernate Mode

In Hibernate mode, all the clocks supplied to internal peripheral units other than RTC/ICU/PMU and to the CPU

core are fixed to high level.

To switch to Hibernate mode from Fullspeed mode, first execute the HIBERNATE instruction. The VR4102 waits

until the SysAD bus (internal) enters idle status after the completion of the WB stage of the HIBERNATE instruction,

DRAM has entered self-refresh mode, and the MPOWER pin has been made inactive. Then, the internal clocks

(including TClock and MasterOut) are shut down, and the pipeline stops. PLL also stops, but RTC continue to

operate.

In Hibernate mode, the processor returns to Fullspeed mode when it is alarmed from the RTC, the power-on

switch is pressed, or DCD# pin is asserted. At this time, the contents of bits indicating the states of pins in the

peripheral unit’s registers and caches in the CPU core are undefined. The contents of other fields are retained.

15.2 REGISTER SET

The PMU registers are listed below.

Table 15-4. PMU Registers

Address

R/W

Function

0x0B00 00A0

R/W

PMUINTREG

PMU Interrupt/Status Register

0x0B00 00A2

R/W

PMUCNTREG

PMU Control Register

0x0B00 00A4

R/W

PMUINT2REG

PMU Interrupt Register 2

0x0B00 00A6

R/W

PMUCNT2REG

PMU Control Register 2

Each register is described in detail below.

VR4102 Datasheet(PDF) 327 Page - NEC