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VR4102 Datasheet(PDF) 332 Page - NEC |
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VR4102 Datasheet(HTML) 332 Page - NEC |
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332 / 701 page ![]() CHAPTER 15 PMU (POWER MANAGEMENT UNIT) 332 15.2.3 PMUINT2REG (0x0B00 00A4) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name GPIO12INTR GPIO11INTR GPIO10INTR GPIO9INTR Reserved Reserved Reserved Reserved R/W R/W R/W R/W R/W R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit D7 D6D5 D4D3D2 D1 D0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R/W R RR RRR R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D[15] GPIO12INTR GPIO[12] activation interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected D[14] GPIO11INTR GPIO[11] activation interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected D[13] GPIO10INTR GPIO[10] activation interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected D[12] GPIO9INTR GPIO[9] activation interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected D[11:0] Reserved Write 0 when writing. 0 is returned after a read. This register is used to specify whether the GPIO[12:9] interrupt is detected as a power-on factor. |
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