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VR4102 Datasheet(PDF) 369 Page - NEC |
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VR4102 Datasheet(HTML) 369 Page - NEC |
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369 / 701 page  CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 369 18.2.7 GIUINTENL (0x0B00 010C) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name INTE[15] INTE[14] INTE[13] INTE[12] INTE[11] INTE[10] INTE[9] INTE[8] R/W R/W R/W R/W R/W R/W R/W R/W R/W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit D7 D6D5 D4D3D2 D1 D0 Name INTE[7] INTE[6] INTE[5] INTE[4] INTE[3] INTE[2] INTE[1] INTE[0] R/W R/W R/W R/W R/W R/W R/W R/W R/W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D[15..0] INTE[15..0] Interrupt enable to GPIO pin 1 : Interrupt enable 0 : Interrupt prohibit This register is used to set interrupt enable status for GPIO pins. The INTE[15..0] bits correspond to the GPIO[15..0] pins. When “1” is set to the corresponding INTE bit, interrupts are enabled for the corresponding GPIO pins. Caution The function of GPIO[15] is fixed as DCD# signal input. |
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