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VR4102 Datasheet(PDF) 370 Page - NEC |
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VR4102 Datasheet(HTML) 370 Page - NEC |
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370 / 701 page  CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 370 18.2.8 GIUINTENH (0x0B00 010E) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name INTE[31] INTE[30] INTE[29] INTE[28] INTE[27] INTE[26] INTE[25] INTE[24] R/W R/W R/W R/W R/W R/W R/W R/W R/W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit D7 D6D5 D4D3D2 D1 D0 Name INTE[23] INTE[22] INTE[21] INTE[20] INTE[19] INTE[18] INTE[17] INTE[16] R/W R/W R/W R/W R/W R/W R/W R/W R/W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D[15..0] INTE[31..16] Interrupt enable to GPIO pin 1 : Interrupt enable 0 : Interrupt prohibit This register is used to set interrupt enable status for GPIO pins. The INTE[31..16] bits correspond to the GPIO[31..16] pins. When “1” is set to the corresponding INTE bit, interrupts are enabled for the corresponding GPIO pins. |
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