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VR4102 Datasheet(PDF) 374 Page - NEC |
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VR4102 Datasheet(HTML) 374 Page - NEC |
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374 / 701 page ![]() CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT) 374 18.2.12 GIUINTALSELH (0x0B00 0116) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name INTL[31] INTL[30] INTL[29] INTL[28] INTL[27] INTL[26] INTL[25] INTL[24] R/W R/W R/W R/W R/W R/W R/W R/W R/W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit D7 D6D5 D4D3D2 D1 D0 Name INTL[23] INTL[22] INTL[21] INTL[20] INTL[19] INTL[18] INTL[17] INTL[16] R/W R/W R/W R/W R/W R/W R/W R/W R/W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D[15..0] INTL[31..16] Interrupt setting during level detection method 1 : High active 0 : Low active This register is used to set the active level when using the level detection method for interrupts to GPIO pins. The INTL[31..16] bits correspond to the GPIO[31..16] pins. When “1” is set to the corresponding INTL bit, the high-active level detection method is used for interrupts at the corresponding GPIO pin. The low-active level detection method is used when “0” is set to this bit. The contents of this register are not reflected when the edge detection method is selected via the GIUINTTYPH register (GPIO Interrupt Type (Edge or Level) Select Register). When using this register, be sure to set the level detection method via the GIUINTTYPH register (GPIO Interrupt Type (Edge or Level) Select Register). |
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