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FXLS93421 Datasheet(PDF) 38 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 38 Page - NXP Semiconductors |
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38 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_min, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified # Characteristic Symbol Min Typ Max Units Test notes Oscillator Training (Section 11.5.1) 10932 Oscillator Training Time tOscTrain — 4 — ms 7, 8 10942 Oscillator Cycles in Training Time nOSC_4ms_TYP — 40000 — 1/fOSC 7, 8 10944 Oscillator Training Window OscTrainWIN 38000 — 42000 1/fOSC 7, 8 10943 Oscillator Training Adjustment Threshold OscTrainADJ –400 — 400 1/fOSC 7, 8 10941 Oscillator Training Step Size OscTrainRES 250 1/fOSC 7, 8 10946 Quiescent Current Settling Time (Power Applied to Iq = IIDLE ± 2 mA) tSET — — 4 ms 7, 9 BUS_I Micro-cut 10931 Survival Time (BUS_I disconnect without Reset, CBUF=1 µF, Bus with 1 slave) tBUS_I_MICROCUT 30 — — µs 7, 9 10952 Reset Time (BUS_I disconnect time to Reset, CBUF=1 µF, Bus with 1 slave) tBUS_I_RESET — — 1000 µs 7, 9 10953 Survival Time (BUS_I disconnect without Reset, CBUF=470 nF, Bus with 1 slave) tBUS_I_MICROCUT 15 — — µs 7, 9 10954 Reset Time (BUS_I disconnect time to Reset, CBUF=470 nF, Bus with 1 slave) tBUS_I_RESET — — 1000 µs 7, 9 BUS_I Undervoltage Detection Delay 10947 BUS_I < VBUS_I_UV_F to IRESP Deactivation tBUS_I_POR — — 5 µs 7 VBUF Undervoltage Detection Delay 10958 VBUF < VBUF_UV_F to IRESP Deactivation tVBUF_POR — — 5 µs 7 10957 Undervoltage/Overvoltage Recovery Delay tUVOV_RCV — 100 — µs 7 VBUF Capacitor Monitor 36817 DSI Command Start to Capacitor Test tD_CAPTEST — 3.0 — µs 7 36821 PSI5 Synchronous Command Start to Capacitor Test tP_CAPTEST — 9.2 — µs 7 36823 PSI5 Asynchronous Response Start to Capacitor Test tA_CAPTEST — 179.2 — µs 7 36822 Capacitor Test Disconnect Time tCAPTST_TIME — 1 — µs 7 Table 43. Dynamic electrical characteristics - supply and support circuitry...continued 11 Functional description 11.1 User accessible data array A user accessible data array allows for each device to be customized. The array consists of an OTP factory programmable block, an OTP user programmable block, and read- only registers for data and device status. The OTP blocks incorporate independent data verification. 11.1.1 User accessible data - general device information Bit Type Address Register 7 6 5 4 3 2 1 0 R $00 COUNT COUNT[7:0] R $01 DEVSTAT CH0_ERR CH1_ERR COMM_ERR MEMTEMP_ERR SUPPLY_ERR TESTMODE DEVRES DEVINIT R $02 DEVSTAT1 VBUFUV_ERR BUSINUV_ERR VBUFOV_ERR RESERVED INTREGA_ERR INTREG_ERR INTREGF_ERR CONT_ERR R $03 DEVSTAT2 F_OTP_ERR U_OTP_ERR U_RW_ERR U_W_ACTIVE TEMP1_ERR TEMP0_ERR RESERVED RESERVED Table 44. User accessible data - general device information FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 38 / 254 |
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