FXLS93421 datasheet(51/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

11.2.5 Temperature register (TEMPERATURE)

The temperature register is a read-only register which provides a temperature value from

the channel 0 temperature sensor. The temperature value is specified in Section 10.5.

Note, the device is only guaranteed to operate within the temperature limits specified in

Section 10. This includes the performance of the temperature register values.

This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming

Mode.

Location

Bit

Address

$0E

TEMPE

RATURE

TEMP[7:0]

Reset Value

Table 74. Temperature register (TEMPERATURE)

11.2.6 Device lock register (DEVLOCK_WR)

The device lock register is a user programmed read/write register which contains the

ENDINIT bit and reset control bits.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$10

DEVLOCK_WR

ENDINIT

RESERVED

SUP_ERR_DIS

RESERVED

RESET[1:0]

Reset Value

Table 75. Device lock register (DEVLOCK_WR)

11.2.6.1 End initialization bit (ENDINIT)

The ENDINIT bit is a control bit used to indicate that the user has completed all device

and system level initialization tests. Once the ENDINIT bit is set, writes to all writable

bit can only be cleared by a device reset.

When ENDINIT is set, the following occurs:

• An error detection is enabled for all user writable registers. The error detection code is

continuously calculated on the user writable registers and verified against a previously

calculated error detection code.

• The offset cancellation filter is forced to its final stage.

• Self-test is disabled and inhibited.

• Register Writes are inhibited with the exception of the RESET[1:0] bits in the

DEVLOCK_WR register.

In DSI3 mode, when the ENDINIT bit is set, the device is forced to PDCM according to

the device settings and no longer responds to CRM commands.

In PSI5 mode, the ENDINIT bit is automatically set when the device exits Initialization

Phase 3.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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