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FXLS93421 Datasheet(PDF) 79 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 79 Page - NXP Semiconductors |
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79 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Location Bit Address Register 7 6 5 4 3 2 1 0 Unprogrammed Read Value 1 1 0 0 0 1 0 0 Table 133. Who Am I register...continued The default register value is 0x00. If the register value is 0x00, a value of 0xC4 is transmitted in response to a read command. For all other register values, the actual register value is transmitted in response to a read command. WHO_AM_I Register Value (HEX) Response to a register read command 0X00 0xC4 0X01 Through 0xFF Actual register value Table 134. WHO_AM_I bits 11.2.22 I2C slave address register The I2C slave address register is a user programmed read/write register which contains the unique I2C slave address. The register is readable in all modes. This register is included in the read/write array error detection. This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming Mode. Location Bit Address Register 7 6 5 4 3 2 1 0 $3F I2C_ADDRESS I2C_ADDRESS[7:0] Unprogrammed OTP Value 0 0 0 0 0 0 0 0 Unprogrammed Read Value 0 1 1 0 0 0 0 0 Table 135. I2C slave address register The default register value is 0x00. If the register value is 0x00, the I2C slave address is 0x60 and a value of 0x60 is transmitted in response to a read command. For all other register values, the I2C slave address is the lower 7 bits of the actual register value and the actual register value is transmitted in response to a read command. I2C_ADDRESS register value (HEX) Response to a register read command I2C slave address 0x00, 0x80 0x60 0x60 0x01 Through 0x7F, 0x81 Through 0xFF Actual Register Value I2C_ADDRESS[6:0] Table 136. I2C_ADDRESS bits 11.2.23 Channel 0 and Channel 1 user configuration #1 registers (CH0_CFG_U1, CH1_CFG_U1) The Channel 0 and Channel 1 user configuration #1 registers are user programmable read/write registers which contain channel-specific configuration information. These registers are included in the read/write array error detection. These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5 programming mode. FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 79 / 254 |
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