FXLS93421 datasheet(55/254 Pages) NXP

55 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

2. Write the desired values to the user array registers for only the region to be written

using the procedures in Section 11.2.10.

• The user must take care to ensure that the proper data is written to each region.

If a register write is executed to a new region, the base address changes to the

new region. The previous data written to the register block remains in the shared

registers and is written to OTP if the Write OTP sequence is completed.

3. Execute a write to the WRITE_OTP_EN register with the appropriate bits set for the

desired region to program.

• Once the WRITE_OTP_EN register write is completed, a CRC is calculated for

the data to be written to the region, the register values are written to OTP and the

region is locked from future writes. The UOTP_WR_INIT bit remains set.

4. Delay tOTP_WRITE_MAX to allow the device to complete the writes to OTP.

5. Verify that the OTP write successfully completed by reading back all of the OTP

registers using Register Read commands as defined in Section 11.2.10.

6. Repeat steps 1 through 4 for all regions to be programmed.

The procedure for writing to the user OTP array UF2 region is:

1. Read the CRC_UF2 register and confirm the LOCK_UF2 bit is not set.

2. Write the desired values to the user array registers.

3. Execute a write to the WRITE_OTP_EN register with region 2 selected and the

EX_COMMTYPE and EX_PADDR bit set as desired.

• Once the WRITE_OTP_EN register write is completed, a CRC is calculated for

the data to be written to the region, the register values are written to OTP and the

region is locked from future writes. The UOTP_WR_INIT bit remains set.

4. Delay tOTP_WRITE_MAX to allow the device to complete the writes to OTP and an

automatic read of the UF2 registers from OTP.

5. Verify that the OTP write successfully completed by reading back all of the OTP

registers using Register Read commands.

11.2.8 Bus switch control register (BUSSW_CTRL)

The bus switch control register is a user programmed read/write register which controls

the state of the bus switch output driver. This register is included in the user read/write

array error detection.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$12

BUSSW_CTRL

RESERVED

BUSSW_CTRL[1:0]

Reset Value

Table 79. Bus switch control register (BUSSW_CTRL)

The BUSSW_CTRL bit controls the state of the BUSSW_L pin.

BUSSW_CTRL[1] BUSSW_CTRL[0] BUSSW_L Pin State

High Impedance. An external pullup or pulldown resistor

is required if an external switch is connected

High Impedance. An external pullup or pulldown resistor

is required if an external switch is connected

Table 80. BUSSW_L pin state

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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