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FXLS93421 Datasheet(PDF) 44 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 44 Page - NXP Semiconductors |
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44 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor 11.2.2 Device status registers (DEVSTATx) The device status registers are read-only registers which contain device status information. These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming Mode. Location Bit Address Register 7 6 5 4 3 2 1 0 $01 DEVSTAT CH0_ERR CH1_ERR COMM_ERR MEMTEMP_ ERR SUPPLY_ERR TESTMODE DEVRES DEVINIT Reset Value 1 1 0 0 x 0 1 1 $02 DEVSTAT1 VBUFUV_ERR BUSINUV_ERR VBUFOV_ERR RESERVED INTREGA_ERR INTREG_ERR INTREGF_ERR CONT_ERR Reset Value x x x x x x x 0 $03 DEVSTAT2 F_OTP_ERR U_OTP_ERR U_RW_ERR U_W_ACTIVE TEMP1_ERR TEMP0_ERR RESERVED RESERVED Reset Value 0 0 0 0 0 0 x x $04 DEVSTAT3 MISO_ERR OSCTRAIN_ ERR RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Reset Value 0 0 x x x x x x Table 50. Device status registers (DEVSTATx) 11.2.2.1 Channel 0 error flag (CH0_ERR) The channel 0 error flag is set if a channel 0 specific error is present in the channel 0 DSP: CH0_ERR = CH0_STAT[SIGNALCLIP] | CH0_STAT[ST_INCMPLT] | CH0_STAT[OFFSET_ERR] | CH0_STAT[ST_ERROR] 11.2.2.2 Channel 1 error flag (CH1_ERR) The channel 1 error flag is set if a channel 1 specific error is present in the channel 1 DSP: CH1_ERR = CH1_STAT[SIGNALCLIP] | CH1_STAT[ST_INCMPLT] | CH1_STAT[OFFSET_ERR] | CH1_STAT[ST_ERROR] 11.2.2.3 Communication error flag (COMM_ERR) The communication error flag is set if any bit in DEVSTAT3 is set: COMM_ERR = MISO_ERR | OSCTRAIN_ERR 11.2.2.4 Memory or temperature error flag (MEMTEMP_ERR) The memory error flag is set if any bit in DEVSTAT2 is set: MEMTEMP_ERR = F_OTP_ERR | U_OTP_ERR | U_RW_ERR | U_W_ACTIVE | TEMP1_ERR | TEMP0_ERR 11.2.2.5 Supply error flag (SUPPLY_ERR) The supply error flag is set if any bit in DEVSTAT1 is set: SUPPLY_ERR = VBUFUV_ERR | BUSINUV_ERR | VBUFOV_ERR | INTREG_ERR | INTREGA_ERR | INTREGF_ERR | CONT_ERR A common timer is used for all error bits in the DEVSTAT1 register. If any bit in DEVSTAT1 is set, the timer is reset to tUVOV_RCV. When no supply errors are present, the FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 44 / 254 |
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