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FXLS93421 Datasheet(PDF) 62 Page - NXP Semiconductors

Part # FXLS93421
Description  Dual channel inertial sensor
PDF  254 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS93421 Datasheet(HTML) 62 Page - NXP Semiconductors

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NXP Semiconductors
FXLS9xxxx
Dual channel inertial sensor
In SPI and I2C mode, the PDCMFORMAT bits are readable and writable, but have no
impact on device operation or performance.
11.2.13.3 Source identification (SOURCEID_x)
In SPI mode, the SOURCEID field in the SPI command is compared against the values
in the SOURCEID_x registers. If the SOURCEID field matches one of the values in the
SOURCEID_x registers and the SIDx_EN bit is set for that register, the sensor data
for that SOURCEID is transmitted as shown in Table 92. If more than one enabled
SOURCEID_x register value matches the SOURCEID field in the SPI command a SPI
sensor data request error response is transmitted. If no enabled SOURCEID_X register
value matches the SOURCEID field in the SPI command a SPI sensor data request error
response is transmitted.
Source ID
Source ID enable (SIDx_EN) Transmitted data
0
SPI Error Response
SOURCEID_0
1
CH0_SNSDATA0
0
SPI Error Response
SOURCEID_1
1
CH0_SNSDATA1
0
SPI Error Response
SOURCEID_2
1
CH1_SNSDATA0
0
SPI Error Response
SOURCEID_3
1
CH1_SNSDATA1
Table 92. SPI source identification (SOURCEID_x)
In DSI3 mode, if the SIDx_EN bit in the SOURCEID_x register is set, the associated
SOURCEID value is transmitted in the SOURCEID field of PDCM mode using the
associated transmission time shown in Table 93.
Source ID
Source ID enable
(SIDx_EN)
Transmission time[1]
Transmitted data[2]
0
NA
NA
SOURCEID_0
1
PDCM_RSPST0
CH0_SNSDATA0
0
NA
NA
SOURCEID_1
1
PDCM_RSPST1
CH0_SNSDATA1
0
NA
NA
SOURCEID_2
1
PDCM_RSPST2
CH1_SNSDATA0
0
NA
NA
SOURCEID_3
1
PDCM_RSPST3
CH1_SNSDATA1
Table 93. DSI3 source identification (SOURCEID_x)
[1]
See Section 11.2.18.1 "Periodic data collection mode response start time (PDCM_RSPSTx[12:0])"
[2]
See Section 11.2.25.2 "Channel data type 0 selection bits (CHxDATATYPE0)" and See Section 11.2.25.3 "Channel data
type 1 selection bits (CHxDATATYPE1)"
In PSI5 mode, the SOURCEID_x register SIDx_EN bit values control data transmissions
as shown in Table 94. The SOURCEID_x bits have no effect in PSI5 mode.
FXLS9xxxx
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6 — 8 February 2021
62 / 254



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