FXLS93421 datasheet(66/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Location

Bit

Address

FXLS93xxx

Unprogrammed

Default PSI5 Mode

Table 100. Chip time and bit time register (CHIPTIME)...continued

11.2.15.1 PSI5 self-test repetition bits (ST_RPT[1:0])

In PSI5 mode, the PSI5 self-test repetition bits set the maximum number of PSI5 self-test

repetitions that the device will run before setting the ST_ERROR bit. See Section 6.6.2.5

for details regarding the PSI5 startup self-test.

ST_RPT[1]

ST_RPT[0]

Maximum PSI5 self-test repetitions

Table 101. PSI5 self-test repetition bits (ST_RPT[1:0])

11.2.15.2 PSI5 error latching enable bit (PSI5_ERRLATCH)

In PSI5 mode, the PSI5 error latching enable bit allows for users to disable the automatic

error clearing mechanism for internal faults. When this bit is set, internal errors are

latched until reset. See Section 13.9.4 and Section 13.9.5 for details regarding internal

error handling.

PSI5_

ERRLATCH

PSI5 error handling

Error handling is as specified in Section 11.2.2 and Section 13.9.4

Automatic error clearing is disabled and internal errors are latched until reset as

specified in Section 13.9.5

Table 102. PSI5 error latching enable bit (PSI5_ERRLATCH)

11.2.15.3 Simultaneous sampling enable (SS_EN)

In DSI3 mode, the simultaneous sampling enable bit selects between one of two data

latency methods. See Section 12.4.7 for details regarding sample timing.

SS_EN

Data latency

Synchronous Sampling Mode: Latency relative to transmission start time (PDCM_

RSPST)

Simultaneous Sampling Mode: Latency relative to the start of the Periodic Data

Collection Mode command (falling edge)

Table 103. DSI3 simultaneous sampling enable (SS_EN)

In PSI5 mode, the simultaneous sampling enable bit selects between one of two data

latency methods to accommodate synchronized sampling or simultaneous sampling.

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

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