FXLS93421 datasheet(98/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

data). Both the self-test and offset values are measured with the user scaling set to 1:

U_SNS_SHIFT[1:0] = 0x2 and U_SNS_MULT[7:0] = 0x00.

CH0_STL_P = 0.5 * [CH0_SNSDATA0ST_CTRL=0x8 - CH0_SNSDATA0ST_CTRL=0x0]

CH0_STL_N = 0.5 * [CH0_SNSDATA0ST_CTRL=0x0 - CH0_SNSDATA0ST_CTRL=0x9]

CH0_STH_P = 0.5 * [CH0_SNSDATA0ST_CTRL=0xA - CH0_SNSDATA0ST_CTRL=0x0]

CH0_STH_N = 0.5 * [CH0_SNSDATA0ST_CTRL=0x0 - CH0_SNSDATA0ST_CTRL=0xB]

CH1_STL_P = 0.5 * [CH1_SNSDATA0ST_CTRL=0x8 - CH1_SNSDATA0ST_CTRL=0x0]

CH1_STL_N = 0.5 * [CH1_SNSDATA0ST_CTRL=0x0 - CH1_SNSDATA0ST_CTRL=0x9]

CH1_STH_P = 0.5 * [CH1_SNSDATA0ST_CTRL=0xA - CH1_SNSDATA0ST_CTRL=0x0]

CH1_STH_N = 0.5 * [CH1_SNSDATA0ST_CTRL=0x0 - CH1_SNSDATA0ST_CTRL=0xB]

Two self-test values are stored and available for comparison: a high self-test value and a

low self-test value. The self-test value is controlled by the user via the ST_CTRL[3:0] bits

in the CHx_CFG_U5 registers as described in Section 11.2.27.1.

When self-test is activated, the sensor data can be compared to the values in the

appropriate registers. The difference from the measured deflection value, and the

nominal deflection value stored in the register shall not fall outside the self-test accuracy

limits specified in Section 10.7 (ΔSTACC). See Section 11.6.2 for more details on

calculating the self-test limits.

11.2.38 IC type register

The IC type register is a factory programmable OTP register which contains the IC type

as defined in Table 179. This register is included in the factory programmed OTP array

error detection.

Location

Bit

Address

$C0

ICTYPEID

Table 179. IC type register

11.2.39 IC revision register

The IC revision register is a factory programmable OTP register which contains the IC

revision. The upper nibble contains the main IC revision. The lower nibble contains the

sub IC revision. This register is included in the factory programmed OTP array error

detection.

This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming mode

when ENDINIT is not set. See Section 11.2.10 for details on the register read process for

this register.

Location

Bit

Address

$C1

ICREVID

ICREVID[7:0]

Table 180. IC revision register

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

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