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FXLS93421 Datasheet(PDF) 102 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 102 Page - NXP Semiconductors |
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102 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor Location Bit Address Register 7 6 5 4 3 2 1 0 $D2 TRNS1WFR_X TRNS1WFR_X[7:0] $D3 TRNS1WFR_Y TRNS1WFR_Y[7:0] $D4 TRNS1LOT_L TRNS1LOT_L[7:0] $D5 TRNS1LOT_H TRNS1LOT_H[7:0] $DA TRNS1WFR# TRNS_ASSY_REV[2:0] TRNS1WFR#[4:0] Table 190. Transducer wafer ID registers 11.2.45 User data registers (USERDATA_0 - USERDATA_E) User data registers are user programmable OTP registers which contain user-specific information. These registers are included in the user programmed OTP array error detection. These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming Mode when ENDINIT is not set. See Section 11.2.10 for details on the register read process for these registers. Location Bit Address Register 7 6 5 4 3 2 1 0 $E0 USERDATA_0 USERDATA_0[7:0] $E1 USERDATA_1 USERDATA_1[7:0] $E2 USERDATA_2 USERDATA_2[7:0] $E3 USERDATA_3 USERDATA_3[7:0] $E4 USERDATA_4 USERDATA_4[7:0] $E5 USERDATA_5 USERDATA_5[7:0] $E6 USERDATA_6 USERDATA_6[7:0] $E7 USERDATA_7 USERDATA_7[7:0] $E8 USERDATA_8 USERDATA_8[7:0] $E9 USERDATA_9 USERDATA_9[7:0] $EA USERDATA_A USERDATA_A[7:0] $EB USERDATA_B USERDATA_B[7:0] $EC USERDATA_C USERDATA_C[7:0] $ED USERDATA_D USERDATA_D[7:0] $EE USERDATA_E USERDATA_E[7:0] Unprogrammed OTP Value 0 0 0 0 0 0 0 0 Table 191. User data registers (USERDATA_0 - USERDATA_E) 11.2.45.1 PSI5 initialization phase 2 data transmissions of user data In PSI5 Mode, the values of the user data registers are transmitted in Initialization phase 2 as shown in Table 192. See Section 13.4.2.1 for details on the PSI5 Initialization Phase 2 Transmissions. Location Bit Address Register 7 6 5 4 3 2 1 0 $E0 USERDATA_0 Channel 1 F1: D1 Channel 0 F1: D1 $E1 USERDATA_1 Channel 0 F3: D5 Channel 0 F3: D4 $E2 USERDATA_2 Channel 0 F4: D7 Channel 0 F4: D6 $E3 USERDATA_3 Channel 0 F5: D9 Channel 0 F5: D8 $E4 USERDATA_4 Channel 0 F6: D11 Channel 0 F6: D10 $E5 USERDATA_5 Channel 0 F7: D13 Channel 0 F7: D12 Table 192. PSI5 initialization phase 2 data transmissions of user data FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 102 / 254 |
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