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FXLS93421 Datasheet(PDF) 71 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 71 Page - NXP Semiconductors |
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71 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor 11.2.17.2 PSI5 daisy chain selection bit (DAISY_CHAIN) In PSI5 mode, the transmission mode selection bits select the PSI5 transmission mode as shown in Table 115. DAISY_ CHAIN Operating mode Response (PDCM_ RSTST0) Reference 0 Normal Mode (Asynchronous or Parallel, Synchronous) SNSDATA0 Section 13.5 1 Daisy Chain Mode SNSDATA0 Section 13.8 Table 115. PSI5 daisy chain selection bit (DAISY_CHAIN) In DSI3 mode, the DAISY_CHAIN bit is readable and writable, but has no impact on device operation or performance. In SPI and I2C mode, the DAISY_CHAIN bit is readable and writable, but has no impact on device operation or performance. 11.2.17.3 PSI5 low response current selection bit (PSI5_ILOW) In PSI5 mode, the PSI5 low response current selection bit selects the low PSI5 response current specified in Section 10.4 as shown in Table 116. PSI5_ILOW PSI5 response current 0 Normal Response Current 1 Low Response Current Table 116. PSI5 low response current selection bit (PSI5_ILOW) In DSI3 mode, the PSI5_ILOW bit is readable and writable, but has no impact on device operation or performance. In SPI and I2C mode, the PSI5_ILOW bit is readable and writable, but has no impact on device operation or performance. 11.2.17.4 Dual transmission mode (DUALTRANS) In PSI5 mode, the dual transmission mode bit enables dual data transmission as described in Section 13.7 only if the DAI-SY_CHAIN bit is not set and the ASYNC bit is not set. DUALT RANS SID3_EN SID2_EN SID1_EN SID0_EN Operating mode Response PDCM_RSPST0 Response PDCM_RSPST1 Response PDCM_RSPST2 Response PDCM_RSPST3 Refer ence 0 As specified in Section 11.2.13.3 Normal Mode Asynchronous or Synchronous, Parallel, Daisy Chain CH0_ SNSDATA0 CH0_ SNSDATA1 CH1_ SNSDATA0 CH1_ SNSDATA1 Section 13.5, Section 13.8 x x 0 0 No Transmission None None None None x x 0 1 Dual Data Transmission Mode, Single Transmission CONCATENATE (CH1_SNSDA- TA0, CH0_ SNS-DATA0) None None None x x 1 0 Dual Data Transmission Mode, Single Transmission None CONCATENATE (CH1_SNSDA- TA1, CH0_ SNS-DATA1) None None 1 x x 1 1 Dual Data Transmission Mode, Double Transmission CONCATENATE (CH1_SNSDA- TA0, CH0_ SNS-DATA0) CONCATENATE (CH1_SNSDA- TA1, CH0_ SNS-DATA1) None None Section 13.7 Table 117. Dual transmission mode (DUALTRANS) FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 71 / 254 |
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