FXLS93421 datasheet(94/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

OCPHA

SE[2:0]

Offset cancellation startup phase

Offset low-pass filter frequency

(Hz)

011

Phase 3

2.560

100

Phase 4

0.640

101

Phase 5

0.160

110

Phase 6 / Normal Mode

0.04

111

Not Applicable

Table 169. Offset cancellation phase status (OCPHASE[2:0])...continued

11.2.32.3 Self-test incomplete (ST_INCMPLT)

The self-test incomplete bit is set after a device reset and is cleared when one of the

analog or digital self-tests modes are enabled in the ST_CTRL register (ST_CTRL[3] =

PSI5 internal self-test procedure has started.

ST_

INCMPLT

Condition

An Analog or Digital Self-test has been activated since the last reset

No Analog or Digital Self-test has not been activated since the last reset AND the PSI5 internal self-test

procedure has not completed

Table 170. Self-test incomplete (ST_INCMPLT)

11.2.32.4 Self-test active flag (ST_ACTIVE)

The self-test active bit is set if any self-test mode is currently active, including the PSI5

internal self-test or a self-test voltage is applied to the transducer. The self-test active

bit is cleared when no self-test mode is active and no self-test voltage is applied to the

transducer.

ST_ACTIVE = ST_CTRL[3] | ST_CTRL[2] |ST_CTRL[1] | ST_CTRL[0] | (self-test voltage

applied to transducer)

11.2.32.5 Offset error flag (OFFSET_ERR)

The offset error flag is set if the sensor signal reaches the offset limit specified in

Section 10.6. The OFFSET_ERR bit is cleared on a read of the CHx_STAT register

through any communication interface or on a data transmission that includes the error in

the status field. See Section 11.2.15.2 for details on a method to disable the automatic

clearing of this error in PSI5 mode.

OFFSET_ERR

Error condition

No error detected

Offset error detected

Table 171. Offset error flag (OFFSET_ERR)

11.2.32.6 Self-test error flag (ST_ERROR)

The self-test error flag is set if the PSI5 startup self-test fails as described in Section

6.6.2.5. This bit can only be cleared by a device reset.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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