FXLS93421 datasheet(77/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

11.2.20 SPI configuration control register

In SPI mode, the SPI configuration control register is a user programmed read/write

included in the read/write array error detection.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

programming mode.

Location

Bit

Address

$3D

SPI_CFG

SPI_STATUS

DATASIZE

SPI_CRC_LEN[1:0]

SPICRCSEED[3:0]

Unprogrammed OTP Value

Table 129. SPI configuration control register

11.2.20.1 SPI status reporting selection bit (SPI_STATUS)

The SPI status reporting bit controls the reporting of the SPI basic status as shown in

Table 130. See Section 14.5.

SPI_STATUS

SPI basic status reporting

As documented in Section 14.5.1

As documented in Section 14.5.2

Table 130. SPI status reporting selection bit (SPI_STATUS)

In DSI3 mode, the SPI_STATUS bit is readable and writable, but has no impact on device

operation or performance.

In PSI5 mode, the SPI_STATUS bit is readable and writable, but has no impact on device

operation or performance.

In I2C mode, the SPI_STATUS bit is readable and writable, but has no impact on device

operation or performance.

11.2.20.2 SPI data field size bit (DATASIZE)

The SPI data field size bit controls the size of the SPI data field as shown in Table 131.

See Section 11.6.4.9.

DATASIZE

SPI data field size

12-bits

16-bits

Table 131. SPI data field size bit (DATASIZE)

In DSI3 mode, the DATASIZE bit is readable and writable, but has no impact on device

operation or performance.

In PSI5 mode, the DATASIZE bit is readable and writable, but has no impact on device

operation or performance.

In I2C mode, the DATASIZE bit is readable and writable, but has no impact on device

operation or performance.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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