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LTC2977 Datasheet(PDF) 30 Page - Analog Devices

Part # LTC2977
Description  30V to 58V Input, Dual 30A, Single 60A 關Module Regulator with Digital Power System Management
PDF  138 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTC2977 Datasheet(HTML) 30 Page - Analog Devices

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When switches M2 and M4 are on or it is limited by the
power MOSFET saturation current in the 1st stage, and
M6 and M8 in the 2nd stage:
I=
VCFLYn – VOUTn
RONMn +RONMn
With very low RDS(ON) of the power MOSFETs, the inrush
charge current could easily achieve several hundreds of
Amperes which can be higher than the MOSFET’s Safe
Operating Area (SOA).
The LTM4664A provides a proprietary pre-balance
method to minimize the inrush charging current in voltage
divider applications. The LTM4664A controller detects
the VOUTn pin voltage before switching and compares
it with the VINSn/2 internally. If the VOUTn pin voltage is
much lower than the VINSn/2, a current source will source
95mA current to the VOUTn pin to pull the VOUTn pin up.
If the VOUTn pin voltage is much higher than the VINSn/2,
another current source will sink 50mA from VOUTn pin to
pull the VOUTn pin down.
If the VOUTn pin voltage is close to VINSn/2 and within
the pre-programmed window, both current sources are
disabled and the divider stages start switching. After 68
switching cycles and the VOUTn pin is still within the win-
dow, the FAULTSn pin is released.
For the 4:1 voltage divider with pre-balance startup, the
LTM4664A assumes no load current or very small load
current (less than 50mA) at the VOUTn (output) otherwise
the VOUTn cannot reach VINSn/2 and LTM4664A never
starts up. This no load condition can be achieved by con-
necting the PGOODn pin to the enable pins of the follow-
ing electrical loads. If load current cannot be controlled off
such as resistive loads, a disconnected FETs is required to
disconnect the load to the VOUTn during startup as shown
in the typical applications. The input power source can
operate over the 30V to 58V range, but the supply varia-
tion needs to be constrained to move much slower than
the switching frequency and not exceed the hysteresis set
by the HYS_PRGMSn pin. Large fast voltage excursions
changes will force the 4:1 divider into pre-balance phase.
LTM4664A
30
Rev. 0
For more information www.analog.com
4:1 DIVIDER APPLICATION INFORMATION
A Typical Application in the Figure 1 block diagram shows
the 4:1 voltage divider circuit. For the 1st stage voltage
divider, the VINS1 input voltage is at the drain of very top
MOSFET M1 and the output voltage is at the VOUT1 pin
which is connected to the source of MOSFET M2 and the
drain of MOSFET M3. The output voltage is around half of
the input voltage in steady state. For the 2nd stage voltage
divider, the VINS2 input voltage is at the drain of very top
MOSFET M5 and the output voltage is at the VOUT2 pin
which is connected to the source of MOSFET M6 and the
drain of MOSFET M7. This completes the 4:1 divider.
For divider applications, if the load current is applied
before startup or heavy resistive loads are connected to
the VOUTn pin, the divider stages may not start up due to
the limited drive current of the pre-balance circuit.
Therefore the PGOODS1 signal is used to sequence on
stage 2 RUN2 pin, and the PGOODS2 pin is used to stage
on the dual 25A/30A regulator.
VOLTAGE DIVIDER PRE-BALANCE BEFORE SWITCHING
In voltage divider applications, the VOUTn voltage should
be always close to VINSn/2 in the steady state. The volt-
ages on the flying capacitors (CFLYn) and VOUTn capacitors
are all very close to each other and equal to the half of
the input voltage. The charging inrush current is mini-
mized during each switching cycle because the voltage
difference between capacitors is small. However, without a
special charging method such as the LTM4664A control-
ler pre-charging circuitry, during start-up or fault condi-
tions such as VOUTn short to GND, the difference between
capacitors can be large and huge charging currents may
be large enough to cause very large MOSFETs currents.
When switches M1 and M3 are on in the 1st stage, and
M5 and M7 are on in the 2nd stage. Ideally, the inrush
charge current is:
I=
VINSn – VCFLYn – VOUTn
RONMn +RONMn



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