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LTC2977 Datasheet(PDF) 66 Page - Analog Devices

Part # LTC2977
Description  30V to 58V Input, Dual 30A, Single 60A 關Module Regulator with Digital Power System Management
PDF  138 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTC2977 Datasheet(HTML) 66 Page - Analog Devices

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LTM4664A
66
Rev. 0
For more information www.analog.com
MINIMUM ON-TIME CONSIDERATIONS
Minimum on-time, tON(MIN), is the smallest time duration
that the LTM4664A PSM is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
VOUTn
VINn • fOSC
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTM4664A is 60ns.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
The LTM4664A PSM must enter its run state prior to soft-
start. The RUN_Cn pins are released after the part initial-
izes, and VINS3 is greater than the VIN_ON threshold and
Stage 2 PGood pin releases the RUN_Cn pins. If multiple
LTM4664As are used in an application, they should be
configured to share the same RUN_Cn pins. They all hold
their respective RUN_Cn pins low until all devices initialize
and VINS3 exceeds the VIN_ON threshold for all devices.
The SHARE_CLK pin assures all the devices connected to
the signal use the same time base.
After the RUN_Cn pin releases, the controller waits for the
user-specified turn-on delay (TON_DELAYn) prior to ini-
tiating an output voltage ramp. Multiple LTM4664As and
other LTC parts can be configured to start with variable
delay times. To work correctly, all devices use the same
timing clock (SHARE_CLK) and all devices must share
the RUN_Cn pin.
This allows the relative delay of all parts to be synchro-
nized. The actual variation in the delay will be dependent
on the highest clock rate of the devices connected to the
SHARE_CLK pin (all Analog Devices ICs are configured
to allow the fastest SHARE_CLK signal to control the
timing of all devices). The SHARE_CLK signal can be
±10% in frequency, thus the actual time delays will have
some variance.
Soft-start is performed by actively regulating the load
voltage while digitally ramping the target voltage from 0V
to the commanded voltage set point. The rise time of the
voltage ramp can be programmed using the TON_RISEn
command to minimize inrush currents associated with the
start-up voltage ramp. The soft-start feature is disabled by
setting TON_RISEn to any value less than 0.250ms. The
LTM4664A PSM performs the necessary math internally to
assure the voltage ramp is controlled to the desired slope.
However, the voltage slope can not be any faster than the
VOUTn fundamental limits of the power stage. The number
of tON(MIN) < steps in the ramp is equal to TON_RISE/0.1ms.
Therefore, the shorter the TON_RISEn time setting, the
more discrete steps in the soft-start ramp appear.
The LTM4664A PSM PWM always operates in discon-
tinuous mode during the TON_RISEn operation. In dis-
continuous mode, the bottom MOSFET (MBn) is turned
off as soon as reverse current is detected in the inductor.
This allows the regulator to start up into a prebiased load.
There is no analog tracking feature in the LTM4664A PSM;
however, two outputs can be given the same TON_RISEn
and TON_DELAYn times to achieve ratiometric rail track-
ing. Because the RUNn pins are released at the same time
and both units use the same time base (SHARE_CLK), the
outputs track very closely. If the circuit is in a PolyPhase
configuration, all timing parameters must be the same.
DIGITAL SERVO MODE
For maximum accuracy in the regulated output voltage,
enable the digital servo loop by asserting bit 6 of the
MFR_PWM_MODE command. In digital servo mode, the
LTM4664A PSM will adjust the regulated output voltage
based on the ADC voltage reading. Every 90ms the dig-
ital servo loop will step the LSB of the DAC (nominally
1.375mV or 0.6875mV depending on the voltage range
bit) until the output is at the correct ADC reading. At pow-
er-up this mode engages after TON_MAX_FAULT_LIMIT
unless the limit is set to 0 (infinite). If the TON_MAX_
FAULT_LIMIT is set to  0 (infinite), the servo begins
after TON_RISE is complete and VOUT has exceeded the
DUAL 25A/30A PSM APPLICATIONS INFORMATION



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