LTC2977 datasheet(33/138 Pages) AD

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Design Example

As a design example using LTM4664A divider stages for

a the 4:1 divider at 72W, assume VINS1 = 48V (nominal),

VINS1 = 60V (maximum), VOUT1 = 24V (nominal), IOUT1 =

3A (maximum) for stage 1. For high power and high voltage

applications, always start with a low switching frequency

e.g. 100kHz to minimize the switching losses. To set the

stage 1 to 100kHz switching frequency, a 36.5k 1% resistor

is connected from FREQS1 pin to ground. Set the CFLY1

voltage ripple to be 2% of the output voltage is a good start-

ing point with tradeoff between efficiency and power density.

The CFLY1 can be calculated based on the equation below:

IOUT1(MAX) =3A

CFLY =

IOUT1(MAX)

2• fSW • VCFLY1(RIPPLE)

∼ 31µF =

2•100kHz •0.48V

Consider the ceramic capacitance derating at 24VDC bias

voltage, 8 of 10μF/X7R/50V ceramic capacitors are paral-

leled as flying capacitors.

The 4:1 divider at 72W, assume VINS2 = 24V (nominal),

VIN = 30V (maximum), VOUT2 = 12V (nominal), IOUT2 = 6A

(maximum) for stage 2. For stage 2 start with a switching

frequency of 200kHz to minimize the switching losses. To

set the 200kHz switching frequency, a 60.4k 1% resis-

tor is connected from FREQS2 pin to ground. Set the

CFLY2 voltage ripple to be 2% of the output voltage is a

good starting point with trade-off between efficiency and

is between 0.5V and 1.2V, the internal pre-balance circuit

will source or sink current to the VOUTn pin and regulate

the VOUTn pin to VINSn/2 with around 95mA/50mA capa-

bility. The pre-balance time can be calculated based on the

capacitor CTIMERSn on the TIMERSn pin: TPRE-BALANCE =

CTIMER • 0.7V/7μA, so the pre-balance time is 100ms/μF

(e.g. the pre-balance time is 10ms with 0.1μF CTIMER). For

voltage divider applications, if the flying capacitor CFLYn

and the VOUTn capacitor are very large and input voltage

is high, it may take several pre-balance time periods to

pre-balance the VOUTn pin to VINSn/2 with a fixed CTIMER.

A longer start-up time is expected. Assuming zero initial

conditions, the time to charge the capacitors, τcharge can

be estimated from the equation:

τCharge =(COUT +CFLY)•(VIN / 2/ 93mA)

Keep in mind that the approximate capacitor value will be

the value at both voltage bias and temperature, this infor-

mation can be derived from the capacitor data sheet curves.

Input/Output Capacitor and Flying Capacitor Selection

In high power switched capacitor applications, large AC

currents flow through the flying capacitors and input/

output capacitors. Low ESR ceramic capacitors are

highly recommended for high power switch capacitor

applications.

Make sure the maximum RMS capacitor current is within

the spec or higher rated capacitors are preferred. Note

that capacitor manufacturers’ ripple current ratings are

often based on only 2000 hours of life. This makes it

advisable to further derate the capacitor.

LTM4664A

Rev. 0

For more information www.analog.com

4:1 DIVIDER APPLICATION INFORMATION

4664A F07

FAULT

LOW

3.5µA CHARGE

TIMER PIN

3.5µA CHARGE

TIMER PIN

7µA CHARGE

TIMER PIN

0.5V

1.2V

PRE-BALANCE TIME

TURN ON

TIME

FAULT

RELEASE

Figure 7. Timer Behavior During Fault or Startup

LTC2977 Datasheet(PDF) 33 Page - Analog Devices

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