LTC2977 datasheet(64/138 Pages) AD

64 / 138 page

LTM4664A

Rev. 0

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DUAL 25A/30A PSM APPLICATIONS INFORMATION

current comparator, IREV, turns off the bottom MOSFET

(MBn) just before the inductor current reaches zero, pre-

venting it from reversing and going negative. Thus, the

controller can operate in discontinuous (pulse-skipping)

operation. In forced continuous operation, the induc-

tor current is allowed to reverse at light loads or under

large transient conditions. The peak inductor current is

determined solely by the voltage on the COMP_Cna pin.

In this mode, the efficiency at light loads is lower than

in discontinuous mode operation. However, continuous

mode exhibits lower output ripple and less interference

with audio circuitry. Forced continuous conduction mode

may result in reverse inductor current, which can cause

the input supply to boost. The VIN_OV_FAULT_LIMIT

can detect this on VIN3 and turn off the offending chan-

nel. However, this fault is based on an ADC read and can

nominally take up to 100ms to detect. If there is a concern

about the input supply boosting, keep the part in discon-

tinuous conduction operation.

SWITCHING FREQUENCY AND PHASE

The switching frequency of the LTM4664A’s PSM chan-

nels is established by its analog phase-locked-loop (PLL)

locking on to the clock present at the module’s SYNC pin.

The clock waveform on the SYNC pin can be generated by

the LTM4664A’s PSM internal circuitry when an external

pull-up resistor to 3.3V (e.g., VDD33) is provided, in combi-

nation with the LTM4664A PSM control IC’s FREQUENCY_

SWITCH command being set to one of the following sup-

ported values: 250kHz, 350kHz, 425kHz, 500kHz, 575kHz,

650kHz, 750kHz. In this configuration, the module is called

a “sync master”: (using the factory-default setting of MFR_

CONFIG_ALL[4] = 0b), SYNC becomes a bidirectional

open-drain pin, and the LTM4664A PSM pulls SYNC logic

low for nominally 500ns at a time, at the prescribed clock

rate. The SYNC signal can be bused to other LTM4664A

PSM device modules (configured as “sync slaves”), for

purposes of synchronizing switching frequencies of mul-

tiple modules within a system—but only one LTM4664A

PSM devices should be configured as a “sync master”; the

other LTM4664A(s) should be configured as “sync slaves”.

The most straightforward way is to set its

FREQUENCY_ SWITCH command to 0x0000 and

MFR_CONFIG_ALL[4] = 1b. This can be easily imple-

mented with resistor pin-strap settings on the FSWPH_

CFG pin (see Table 3). Using MFR_CONFIG_ALL[4] = 1b,

the LTM4664As SYNC pin becomes a high impedance

input, only—i.e., it does not drive SYNC low. The module

synchronizes its frequency to that of the clock applied to

its SYNC pin. The only shortcoming of this approach is:

in the absence of an externally applied clock, the switch-

ing frequency of the module will default to the low end of

its frequency-synchronization capture range (~225kHz).

If fault-tolerance to the loss of an externally applied SYNC

clock is desired, the FREQUENCY_SWITCH command of

a “sync slave” can be left at the nominal target switching

frequency of the application, and not 0x0000 However,

it is then still necessary to configure MFR_CONFIG_

ALL[4] = 1b. With this combination of configurations,

the LTM4664A’s SYNC pin becomes a high impedance

input and the module synchronizes its frequency to

that of the externally applied clock, provided that the

frequency of the externally applied clock exceeds ~½.

of the target frequency (FREQUENCY_SWITCH). If the

SYNC clock is absent, the module responds by operating

at its target frequency, indefinitely. If and when the SYNC

clock is restored, the module automatically phase-locks

to the SYNC clock as normal. The only shortcoming of

this approach is: the EEPROM must be configured per

above guidance; resistor pin-strapping options on the

FSWPH_CFG pin alone cannot provide fault-tolerance to

the absence of the SYNC clock.

The FREQUENCY_SWITCH register can be altered via I2C

commands, but only when switching action is disengaged,

i.e., the module’s outputs are turned off. The FREQUENCY_

SWITCH command takes on the value stored in NVM at

VINS3 power-up, but is overridden according to a resis-

tor pin-strap applied between the FSWPH_CFG pin and

SGND only if the module is configured to respect resistor

pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 3

highlights available resistor pin-strap and corresponding

FREQUENCY_SWITCH settings.

The relative phasing of all active channels in a PolyPhase

rail should be optimally phased. The relative phasing of

each rail is 360°/n, where n is the number of phases in the

rail. MFR_PWM_CONFIG[2:0] configures channel relative

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