LTC2977 datasheet(40/138 Pages) AD

40 / 138 page

LTM4664A

Rev. 0

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up to tCONVERT to detect. If there is a concern about the

input supply boosting, keep the part in discontinuous

conduction mode.

If the part is set to discontinuous mode operation, as

the inductor average current increases, the controller will

automatically modify the operation from discontinuous

mode to continuous mode.

SWITCHING FREQUENCY AND PHASE

The switching frequency of the PWM_C1 can be estab-

lished with an internal oscillator or an external time base.

The internal phase-locked loop (PLL) synchronizes the

PWM control to this timing reference with proper phase

relation, whether the clock is provided internally or exter-

nally. The device can also be configured to provide the

master clock to other devices through PMBus command,

NVM setting, or external configuration resistors as out-

lined in Table 3.

As clock master, a LTM4664A PSM device will drive its

open-drain SYNC pin at the selected rate with a pulse width

of 500ns. An external pull-up resistor between SYNC and

VDD33 is required in this case. Only one device connected

to SYNC should be designated to drive the pin. The other

LTM4664A PSM devices will automatically revert to an

external SYNC input, disabling its own SYNC, as long as

the external SYNC frequency is greater than 80% of the

programmed SYNC frequency. The external SYNC input

shall have a duty cycle between 20% and 80%.

Whether configured to drive SYNC or not, the LTM4664A

PSM devices can continue PWM operation using its own

internal oscillator if an external clock signal is subse-

quently lost.

The device can also be programmed to always require an

external oscillator for PWM operation by setting bit 4 of

MFR_CONFIG_ALL. The status of the SYNC driver circuit

is indicated by bit 10 of MFR_PADS.

The MFR_PWM_CONFIG command can be used to con-

figure the phase of each channel. Desired phase can also

be set from EEPROM or external configuration resistors

as outlined in Table 3. Designated phase is the relationship

between the falling edge of SYNC and the internal clock

edge that sets the PWM latch to turn on the top power

switch. Additional small propagation delays to the PWM

control pins will also apply. Both PSM channels must be

off before the FREQUENCY_SWITCH and MFR_PWM_

CONFIG commands can be written to the LTM4664A PSM.

The phase relationships and frequency options provide

for numerous application options. Multiple LTM4664A

PSM channels modules can be synchronized to realize a

PolyPhase array. In this case the phases should be sepa-

rated by 360/n degrees, where n is the number of phases

driving the output voltage rail.

PWM LOOP COMPENSATION

The internal PWM loop compensation resistors RCOMPna

of the LTM4664A PSM can be adjusted using bit[4:0] of

the MFR_PWM_COMP command.

The transconductance (gm) of the LTM4664A PSM chan-

nel PWM error amplifier can be adjusted using bit[7:5]

of the MFR_PWM_COMP command. These two loop

compensation parameters can be programmed when

the device is in operation. Refer to the Programmable

Loop Compensation subsection in the Dual 25A/30A PSM

Applications Information section for further details.

OUTPUT VOLTAGE SENSING

Both PSM channels in LTM4664A have differential ampli-

fiers, which allow the remote sensing of the load voltage

between V+ and V– pins. The telemetry ADC is also fully

differential and makes measurements between VOSNS+_

Cn and VOSNS–_Cn voltages for both channels at the V+

and V– pins, respectively. The maximum allowed is 1.5V,

but the LTM4664A design is limited to 1.8V.

INTVCC/EXTVCC POWER

Power for the internal MOSFET drivers and most other

internal circuitry is derived from the INTVCC pin. When the

EXTVCC pin is shorted to GND or tied to a voltage less than

4.7V, an internal 5.5V linear regulator supplies INTVCC

power from VINS3. If EXTVCC is taken above approximately

4.7V and VINS3_C1 is higher than 7.0V, the 5.5V regu-

lator is turned off and an internal switch is turned on,

DUAL 25A/30A PSM OPERATION

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