LTC2977 datasheet(52/138 Pages) AD

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LTM4664A

Rev. 0

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The user is encouraged to use as high a clock rate as

possible to maintain efficient data packet transfer between

all devices sharing the serial bus interface. The LTM4664A

PSM supports the full PMBus frequency range from

10kHz to 400kHz.

SIMILARITY BETWEEN PMBus, SMBus AND I2C

2-WIRE INTERFACE

The PMBus 2-wire interface is an incremental extension

of the SMBus. SMBus is built upon I2C with some minor

differences in timing, DC parameters and protocol. The

PMBus/SMBus protocols are more robust than simple

I2C byte commands because PMBus/SMBus provide

timeouts to prevent persistent bus errors and optional

packet error checking (PEC) to ensure data integrity. In

general, a master device that can be configured for I2C

communication can be used for PMBus communication

with little or no change to hardware or firmware. Repeat

start (restart) is not supported by all I2C controllers but

is required for SMBus/PMBus reads. If a general purpose

I2C controller is used, check that repeat start is supported.

The LTM4664A PSM supports the maximum SMBus

clock speed of 100kHz and is compatible with the higher

speed PMBus specification (between 100kHz and 400kHz)

if MFR_ COMMON polling or clock stretching is enabled.

For robust communication and operation refer to the Note

section in the PMBus command summary. Clock stretch-

ing is enabled by asserting bit 1 of MFR_CONFIG_ALL.

For a description of the minor extensions and exceptions

PMBus makes to SMBus, refer to PMBus Specification

Part 1 Revision 1.2: Paragraph 5: Transport.

For a description of the differences between SMBus

and I2C, refer to System Management Bus (SMBus)

Specification Version 2.0: Appendix B—Differences

Between SMBus and I2C.

PMBus SERIAL DIGITAL INTERFACE

The LTM4664A PSM communicates with a host (master)

using the standard PMBus serial bus interface. The Timing

Diagram, Figure 10, shows the timing relationship of the

signals on the bus. The two-bus lines, SDA and SCL, must

be high when the bus is not in use. External pull-up resis-

tors or current sources are required on these lines. The

LTM4664A is a slave device. The master can communicate

with the LTM4664A using the following formats:

Master Transmitter, Slave Receiver

Master Receiver, Slave Transmitter

The following PMBus protocols are supported:

Write Byte, Write Word, Send Byte

Read Byte, Read Word, Block Read, Block Write

Alert Response Address

Figure 11 thru Figure 28 illustrate the aforementioned

PMBus protocols. All transactions support PEC and GCP

(group command protocol). The Block Read supports 255

bytes of returned data. For this reason, the PMBus time-

out may be extended when reading the fault log.

Figure 11 is a key to the protocol diagrams in this section.

PEC is optional.

A value shown below a field in the following figures is

mandatory value for that field.

The data formats implemented by PMBus are:

Master transmitter transmits to slave receiver. The

transfer direction in this case is not changed.

Master reads slave immediately after the first byte. At

the moment of the first acknowledgment (provided by

the slave receiver) the master transmitter becomes a

master receiver and the slave receiver becomes a slave

transmitter.

Combined format. During a change of direction within

a transfer, the master repeats both a start condition

and the slave address but with the R/Wbit reversed. In

this case, the master receiver terminates the transfer

by generating a NACK on the last byte of the transfer

and a STOP condition.

DUAL 25A/30A PSM OPERATION

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