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LTC2977 Datasheet(PDF) 14 Page - Analog Devices

Part # LTC2977
Description  30V to 58V Input, Dual 30A, Single 60A 關Module Regulator with Digital Power System Management
PDF  138 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTC2977 Datasheet(HTML) 14 Page - Analog Devices

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LTM4664A
14
Rev. 0
For more information www.analog.com
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. All voltages are referred to GND pin unless
otherwise specified.
Note 2: The LTM4664A is tested under pulsed load conditions such that
TJ ≈ TA. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 3: All Currents into the device pins are positive, all currents out of
the device are negative. Each channel of PSM is tested independently in
production. A shorthand notation is used in this document that allows
these parameters to be referred to by “VINS3_Cn" and “VOUTCn”, where n
is permitted to take on a value of 0 or 1. This italicized “n” notation and
convention is extended to encompass all such pin names, as well as
register names with channel-specific, i.e., paged data. For example, VOUT_
COMMANDn refers to the VOUT_COMMAND command code data located
in Pages 0 and 1, which in turn relate to channel 0 (VOUTC0) and channel 1
(VOUTC1). Registers containing non-page-specific data, i.e., whose data is
“global” to the module or applies to both of the module’s channels lack the
italicized, “n”, e.g., FREQUENCY_SWITCH.
Note 4: See output current derating curves for different VIN, VOUT, Load
Current and TA, located in the Dual 25A/30A PSM Applications Information
section. For output voltage up to 1.2V, Dual 30A loads are rated.
Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits
mantissa (signed). This limits the output resolution to 10 bits though the
internal ADC is 16 bits and the calculations use 32-bit words.
Note 6: VOUTCn (DC) and line and load regulation tests are performed
in production with digital servo disengaged (MFR_PWM_MODEn[6] =
0b) and low VOUTCn range selected MFR_PWM_MODEn[1] = 1b. The
digital servo control loop is exercised in production (setting MFR_PWM_
MODEn[6] = 1b), but convergence of the output voltage to its final settling
value is not necessarily observed in final test—due to potentially long
time constants involved—and is instead guaranteed by the output voltage
readback accuracy specification. Evaluation in application demonstrates
capability; see the Typical Performance Characteristics section.
Note 7: These typical parameters are based on bench measurements and
are not production tested.
Note 8: Even though VOUTC0 and VOUTC1 are specified for 3.6V absolute
maximum, the maximum recommended command voltage to regulate
output channels 0 and 1 is 1.5V with VOUT range-setting bit set using
MFR_PWM_MODEn[1].
Note 9: Channel n OV/UV comparator threshold accuracy for MFR_PWM_
MODEn[1] = 1b tested in ATE at VVOSNS+_Cn – VVOSNS–Cn = 0.5V and
2.7V. MFR_PWM_MODEn[1] = 1b is the Low Range.
Note 10: Tested at IC-level ATE
Note 11: The absolute maximum rating for the VINS3 pin is 18V. Input
voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled
down from the VINS3 pin.
Note 12: The data conversion is done by default in round robin fashion.
All inputs signals are continuously converted for a typical latency of 90ms.
Setting MFR_ADC_CONTRL value to be 0 to 12, LTM4664A can do fast
data conversion with only 8ms to 10ms. See section PMBus Command
for details.
Note 13: Part tested with PWM disabled. Evaluation in application
demonstrates capability. TUE(%) = ADC Gain Error (%) +100 • (Zero code
Offset + ADC Linearity Error)/Actual Value.
Note 14: EEPROM endurance and retention are guaranteed by wafer-level
testing for data retention. The minimum retention specification applies
for devices whose EEPROM has been cycled less than the minimum
endurance specification, and whose EEPROM data was written to at 0°C
≤ TJ ≤ 85°C. The RESTORE_USER_ALL or MFR_RESET is valid over
the entire operating temperature range and does not influence EEPROM
characteristics.
Note 15: Write operations above TJ = 85°C or below 0°C are possible
although the Electrical Characteristics are not guaranteed and the EEPROM
will be degraded. Read operations performed at temperatures below 125°C
will not degrade the EEPROM Writing to the EEPROM above 85°C will
result in a degradation of retention characteristics.
Note 16: M1-M8 power MOSFET are final tested separately before
assembly in to the µModule.
Note 17: MFR_PWM_MODE[2] = 1 or 0 sets device in low DCR mode or
regular DCR mode respectively. MFR_PWM_MODE[7]=1 or 0 sets device in
high output current range or low current range. See “Output Current Sensing
and sub milliohm DCR Current Sensing” in Operation Section for details.
Only VILIMIT codes 2–8 are supported for DCR sensing.
ELECTRICAL CHARACTERISTICS



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