LTC2977 datasheet(48/138 Pages) AD

48 / 138 page

LTM4664A

Rev. 0

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Mapping Faults to FAULT Pins

Channel-to-channel fault (including channels from multiple

LTM4664A PSMs) dependencies can be created by con-

necting FAULT_Cn pins together. In the event of an internal

fault, one or more of the channels is configured to pull the

bussed FAULT_Cn pins low. The other channels are then

configured to shut down when the FAULT_Cn pins are

pulled low. For autonomous group retry, the faulted chan-

nel is configured to let go of the FAULT_Cn pin(s) after a

retry interval, assuming the original fault has cleared. All

the channels in the group then begin a soft-start sequence.

If the fault response is LATCH_OFF, the FAULT_Cn pin

remains asserted low until either the RUN_Cn pin is tog-

gled OFF/ON or the part is commanded OFF/ON. The tog-

gling of the RUN_Cn either by the pin or OFF/ON command

will clear faults associated with the channel. If it is desired

to have all faults cleared when either RUN_Cn pin is tog-

gled or, set bit 0 of MFR_CONFIG_ALL to a 1.

The status of all faults and warnings is summarized in the

STATUS_WORD and STATUS_BYTE commands.

Additional fault detection and handling capabilities are:

See Table 18.

Power Good Pins

The PGOOD_Cn pins of the LTM4664A PSM are con-

nected to the open drains of internal MOSFETs. The

MOSFETs turn on and pull the PGOOD_Cn pins low when

the channel output voltage is not within the channel’s

UV and OV voltage thresholds. During TON_DELAY and

TON_RISE sequencing, the PGOOD_Cn pin is held low.

The PGOOD_Cn pin is also pulled low when the respective

RUN_Cn pin is low. The PGOOD_Cn pin response is deg-

litched by an internal 100µs digital filter. The PGOOD_Cn

pin and PGOOD status may be different at times due to

communication latency of up to 10µs.

CRC Protection

The integrity of the NVM memory is checked after a power

on reset. A CRC error will prevent the controller from leav-

ing the inactive state. If a CRC error occurs, the CML bit is

set in the STATUS_BYTE and STATUS_WORD commands,

the appropriate bit is set in the STATUS_MFR_SPECIFIC

command, and the ALERT pin will be pulled low. NVM

repair can be attempted by writing the desired configura-

tion to the controller and executing a STORE_USER_ALL

command followed by a CLEAR_FAULTS command.

The LTM4664A manufacturing section of the NVM is

mirrored. If both copies are corrupted, the “NVM CRC

Fault” in the STATUS_MFR_SPECIFIC command is set.

If this bit remains set after being cleared by issuing a

CLEAR_FAULTS or writing a 1 to this bit, an irrecoverable

internal fault has occurred. The user is cautioned to dis-

able both output power supply rails associated with this

specific part. There are no provisions for field repair of

NVM faults in the manufacturing section.

SERIAL INTERFACE

The LTM4664A serial interface is a PMBus compliant

slave device and can operate at any frequency between

10kHz and 400kHz. The address is configurable using

either the NVM or an external resistor divider. In addition

the LTM4664A always responds to the global broadcast

address of 0x5A (7-bit) or 0x5B (7-bit).

The serial interface supports the following protocols defined

in the PMBus specifications: 1) send command, 2) write byte,

3) write word, 4) group, 5) read byte, 6) read word and 7) read

block. 8) write block. All read operations will return a valid

PEC if the PMBus master requests it. If the PEC_REQUIRED

bit is set in the MFR_CONFIG_ALL command, the PMBus

write operations will not be acted upon until a valid PEC has

been received by the LTM4664A.

Communication Protection

PEC write errors (if PEC_REQUIRED is active), attempts

to access unsupported commands, or writing invalid data

to supported commands will result in a CML fault. The

CML bit is set in the STATUS_BYTE and STATUS_WORD

commands, the appropriate bit is set in the STATUS_CML

command, and the ALERT pin is pulled low.

DEVICE ADDRESSING

The LTM4664A PSM offers four different types of addressing

over the PMBus interface, specifically: 1) global, 2) device,

3) rail addressing and 4) alert response address (ARA).

DUAL 25A/30A PSM OPERATION

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