MEC1632 datasheet(162/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 162

 2012-2018 Microchip Technology Inc.

8.6.5

INTERRUPT SOURCE REGISTER

EC_WR

This bit is set autonomously when the EC-to-Host Mailbox Register has been written by the EC at offset 101h. An SIRQ

event or an external nEM_INT event to the Host is generated when any bit in this register (EC_WR or any bit in

EC_SWI[14:0]) is ‘1b’ and the corresponding bit in the Interrupt Mask Register register is ‘1b’.

This bit is automatically cleared by a read of the EC-to-Host Mailbox Register at offset 01h.

EC_SWI[14:0]

Each bit in this field is cleared when written with a ‘1b’. The ability to clear the bit can be disabled if the corresponding

bit in the Host Clear Enable Register is set to ‘0b’.

The EC can generate an interrupt to the Host by setting any bit in this field to ‘1b’. The EC can set bits to ‘1b’ by writing

the corresponding bit in the Interrupt Set Register to ‘1b’.

TABLE 8-9:

INTERRUPT SOURCE REGISTER

HOST OFFSET

Byte 0: 08h

Byte 1: 09h

8-Bit HOST SIZE

EC OFFSET

08h

16-Bit EC SIZE

POWER

VTR

0000h nSYS_RST

DEFAULT

BUS

LPC SPB

BYTE1 BIT

D15

D14

D13

D12

D11

D10

HOST TYPE

R/WC

EC TYPE

R/WC

BIT NAME

EC_SWI[14:7]

BYTE0 BIT

D7D6D5

D4D3

HOST TYPE

R/WC

EC TYPE

R/WC

BIT NAME

EC_SWI[6:0]

EC_WR

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