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QL82SD Device Data Sheet Rev C
Preliminary
14
SERDES Timing Requirements
NOTE: Both Table 14 and Table 15 refer to CDR (10:1) Mode for ChX_txclk and
Channel Link (8:1, 7:1, 4:1) Mode for ClkX_txclk
Figure 17: Serializer Transmit Clock / Deserializer Reference Clock Transition Times
Table 14: Serializer / Transmitter Transmit Clock
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tTCP
Transmit Clock Period
Mode
Dependent
n/a
T
n/a
nS
tTDC
Transmit Clock Duty Cycle
45
50
55
%
tCLKT
Transmit Clock Input Transition Time
Figure 17
1
n/a
n/a
V/nS
tJIT
Transmit Clock Input Jitter
n/a
n/a
150.0
pS
(RMS)
Table 15: Deserializer / Receiver Transmit Clock
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tRFCP
Reference Clock Period
Mode
Dependent
n/a
T
n/a
nS
tRFDC
Reference Clock Duty Cycle
40
50
60
%
tRFCP/tTCP
Ratio of Reference Clock to
Transmit Clock
0.4
0.5
0.6
n/a
tRFTT
Reference Clock Transition Time
Figure 17
1
n/a
n/a
V/nS
90%
90%
10%
10%
txclk
tclkT/tRFTT
tclkT/tRFTT
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