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QL82SD Device Data Sheet Rev C
Preliminary
36
Figure 45: SERDES Logic Cell
RAM Block Description
General Description
The QuickSD device includes multiple dual-port 2,304-bit RAM modules for implementing
RAM and FIFO functions. Each module is user-configurable into four different block
organizations. Modules can also be cascaded horizontally to increase their effective width or
vertically to increase their effective depth as shown in the following figure. The RAM can also
be configured as a modified Harvard Architecture, similar to those found in DSPs.
Figure 46: SERDES 2,304-bit RAM Module
QS
A1
A2
A3
A4
A5
A6
OS
OP
B1
B2
C1
C2
MP
MS
D1
D2
E1
E2
NP
NS
F1
F2
F3
F4
F5
F6
PS
PP
QC
QR
AZ
OZ
QZ
NZ
Q2Z
FZ
MODE [1:0]
WA [9:0]
WD [17:0]
WE
WCLK
RCLK
ASYNCRD
RA [9:0]
RD [17:0]
RE
2,304-bit Module
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