© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
15
www.quicklogic.com
SERDES Switching Characteristics - Serializer/Transmitter]
Table 16: Serializer/Transmitter Switching Characteristics
CDR (10:1) Mode
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tHZD
pad_ChX_p/n High to Tri-State Delay
Figure 18
1.9
2.2
2.5
nS
tLZD
pad_ChX_p/n Low to Tri-State Delay
1.9
2.0
2.2
nS
tZHD
pad_ChX_p/n Tri-State to High Delay
1.9
2.4
3.0
nS
tZLD
pad_ChX_p/n Tri-State to Low Delay
2.0
2.3
2.8
nS
tDIS
ChX_txd[9:0] Setup to ChX_txclk
Figure 19
2.6
3.2
nS
tDIH
ChX_txd[9:0] Hold from ChX_txclk
2.1
2.7
nS
tPLD
Serializer PLL Lock Time
Figure 20
90
uS
Channel Link (8:1, 7:1, 4:1) Mode
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tHZD
pad_ChX_p/n High to Tri-State Delay
Figure 18
1.9
2.2
2.5
nS
tLZD
pad_ChX_p/n Low to Tri-State Delay
1.9
2.0
2.2
nS
tZHD
pad_ChX_p/n Tri-State to High Delay
1.9
2.4
3.0
nS
tZLD
pad_ChX_p/n Tri-State to Low Delay
2.0
2.3
2.8
nS
tDIS
ChX_txd[N-1:0] Setup to ChX_txclk
Figure 21
2.6
3.2
nS
tDIH
ChX_txd[N-1:0] Hold from ChX_txclk
2.1
2.7
nS
tSD
Serializer Delay
1.7
nS
tSCP
Serial Transmit Clock Period
T/mode
nS
tTXD[N-1]
Transmitter Output Pulse Position for
Bit [N-1]
[N-1]
x t
SCP + 1.1
[N-1]
x t
SCP + 1.5
nS
tPLD
Serializer PLL Lock Time
Figure 20
90
uS
Asynchronous Level Conversion (1:1) Mode
tHZD
pad_ChX_p/n High to Tri-State Delay
Figure 18
1.9
2.2
2.5
nS
tLZD
pad_ChX_p/n Low to Tri-State Delay
1.9
2.0
2.2
nS
tZHD
pad_ChX_p/n Tri-State to High Delay
1.9
2.4
3.0
nS
tZLD
pad_ChX_p/n Tri-State to Low Delay
2.0
2.3
2.8
nS
tASD
Asynchronous Serializer Delay -
Data Channel
Figure 22
1.8
nS
tASC
Asynchronous Serializer Delay -
Channel Clock
1.7
nS
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