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© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
3
www.quicklogic.com
General Description
LVDS SERDES Transmitter and Receiver
A QuickSD LVDS SERDES device in serializer mode takes a parallel data bus and a separate
clock and converts them into a serial data stream. In deserializer mode, it takes a serial data
stream and converts it to a configurable bit wide parallel data bus and separate clock. The
reduced number of I/O board traces and cable connectors saves on cost and significantly
simplifies design. Skew and timing issues are significantly reduced and performance is
enhanced. Figure 2 and Figure 3 illustrate the block diagrams of the QuickSD device
transmitter and receiver.
Figure 2: LVDS SERDES Transmitter Block Diagram
Figure 3: LVDS SERDES Receiver Block Diagram
RL = 27 Ω - 100 Ω
Vo +
Vo -
IL = 8-12 mA
Do +
Do -
300k
300k
/Enable
Parallel to Serial
.
.
.
.
txd [9:0]
TTL_Din
Din +
Din -
300k W
300k W
VCM = 0.2 V - 2.2 V
Serial to Parallel
.
.
.
.
FPGA
rxd [9:0]
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