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© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
30
LVDS SERDES Description
LVDS SERDES Applications
The QL82SD device in the QuickLogic QuickSD ESP (Embedded Standard Product) device
family provides a completely integrated configurable Serializer/Deserializer interface solution
combined with 536 K system gates of customizable logic. This device provides a means to
receive and transmit high-speed serial data and implement any proprietary high-speed serial
link.
The QL82SD device is a high performance serializer/deserializer chip. It can be combined
with FIFO buffer memory to build a complete serial link. The need for external FIFOs can be
eliminated by configuring the available internal RAM as two 256 x 36 FIFOs.
The embedded SERDES core is a full duplex design with a serialization section for
transmission and a deserialization section for reception. The transmitter and receiver can be
configured for level conversion (1:1), signals that transmit a clock signal with the data
(1:4, 1:7, 1:8), or applications that require clock recovery (1:10).
The embedded SERDES core has a system interface that emulates a synchronous FIFO for
ease of use. FIFOs allow maximum sustained performance of 600 MB/s running a full duplex
link. Their function is to handle the asynchronous interface between the bus data rate and
the different serial data rates, and handle phase and frequency differences inherent in serial
links. Internal FIFOs of 256
×××× 36 or 512 ×××× 16 can be cascaded with external FIFOs to
expand the buffering to the desired size.
The QL82SD is a versatile part that allows the system designer to create proprietary or
standardized serial links by taking advantage of some, or all, of the embedded features. It has
a number of useful features for system designers of proprietary links with additions of
embedded computational units and customizable I/O.
LVDS SERDES Block Functional Description
The QuickSD SERDES consists of a physical layer for high-speed serial communications,
handling all data translations, clocking and timing. The core is made up of eight data
channels and two channel clocks. These blocks contain the circuitry necessary for all the data
muxing and de-muxing, clock multiplication and division, clock and data phase alignment,
and clock recovery and encoding. The core can be configured to support systems that
transmit a separate clock signal or that have the clock embedded into the data stream and
require clock recovery.
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