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© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
48
LVDS SERDES External Signals
LVDS SERDES Internal Signals (Data Channels 0 to 7)
NOTE:
All Ch0 signals above repeat for Ch1-Ch7. The eight SERDES data channels 0 through 7
are identical.
Table 39: LVDS SERDES External Signals
Signal Name
Description
CH0P, CH0N
LVDS signal pair for data channel 0
CH1P, CH1N
LVDS signal pair for data channel 1
CH2P, CH2N
LVDS signal pair for data channel 2
CH3P, CH3N
LVDS signal pair for data channel 3
CH4P, CH4N
LVDS signal pair for data channel 4
CH5P, CH5N
LVDS signal pair for data channel 5
CH6P, CH6N
LVDS signal pair for data channel 6
CH7P, CH7N
LVDS signal pair for data channel 7
CLKAP, CLKAN
LVDS signal pair for channel clock A
CLKBP, CLKBN
LVDS signal pair for channel clock B
Table 40: LVDS SERDES Internal Signals (Data Channels 0 to 7)
Signal Name
Description
Ch0_rst
Channel 0 Reset Signal
Ch0_oe
Channel 0 Output Enable (1=transmit, 0=receive)
Ch0_en
Channel 0 Enable (reduces power when set to 0)
Ch0_mode[3:0] Channel 0 MODE pins. See the SERDES Data Channel Functional Description
Ch0_txd[9:0]
Channel 0 Parallel Transmit Data Bus
Ch0_txclk
Channel 0 Transmit/Reference Clock
Ch0_sync
Channel 0 Sync Control. When low, a sync pattern is generated on the
CH0_DATA pins to provide a high-speed lock mechanism when using the
embedded clock mode. When high, it will send the data in ChX_txd.
Ch0_rxd[9:0]
Channel 0 Parallel Receive Data Bus
Ch0_rxclk
Channel 0 Receive Clock
Ch0_lock
Channel 0 Lock indicator, to indicate when the SERDES is locked to the serial
bitstream, when using the embedded clock mode.
Ch0_pre_emp
Channel 0 pre-emphasis signal. When high, LVDS transmitter boosts dynamic
current during signal transitions.
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