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© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
29
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RAM Cell Read Timing
Table 28: RAM Cell Synchronous and Asynchronous Read Timing
Figure 42: RAM Cell Synchronous and Asynchronous Read Timing
Symbol
Parameter
Propagation
delay (ns)
RAM Cell Synchronous Read Timing
tSRA
RA setup time to RCLK: the amount of time the READ ADDRESS
must be stable before the active edge of the READ CLOCK
0.686
tHRA
RA hold time to RCLK: the amount of time the READ ADDRESS
must be stable after the active edge of the READ CLOCK
0
tSRE
RE setup time to WCLK: the amount of time the READ ENABLE
must be stable before the active edge of the READ CLOCK
0.243
tHRE
RE hold time to WCLK: the amount of time the READ ENABLE
must be stable after the active edge of the READ CLOCK
0
tRCRD
RCLK to RD: the amount of time between the active READ CLOCK
edge and the time when the data is available at RD
4.38
RAM Cell Asynchronous Read Timing
rPDRD
RA to RD: amount of time between when the READ ADDRESS is
input and when the DATA is output
2.06
RE
RD
RCLK
RA
TSRA
THRA
TSRE
THRE
OLD data
NEW data
TRCRD
RPDRD
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