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© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
17
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Figure 21: Channel Link Mode Serializer Transmit (Using 8:1 Mode as Example)
Figure 22: 1:1 Mode Asynchronous Level Conversion Mode Serializer Delays
[bit3][bit2][bit1][bit0][bit7][bit6][bit5][bit4]
Pad_ClkX_p/n
Pad_ ChX _p/n
TXD
[4]
[5]
[6]
[7]
[0]
ChX
_txd [7:0]
ChX
_txclk
Note:
[N-1]
physical
positions wrt Pad_ClkX_p/n while
Pad_ChX_p/n bit[n]
bit positions wrt ChX
_txd [7:0].
t
t
t
t
TXD
t
TXD
t
TXD
t
TXD
t
TXD
t
DIS
DIH
SD
denotes
refers to
bit
logical
Ch0_txd [0]
Pad_Ch0_p/n
ClkA_txclk
Pad_ClkA_p/n
t
ASD
t
ASC