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QL82SD Device Data Sheet Rev C
Preliminary
22
Super Logic (Flip-Flop and Combinational Circuit) AC Characteristics at
VCC = 2.5 V, TA = 25o C (K = 1)
Figure 28: Super Logic Cell Flip-Flop Structure
Figure 29: Combinational Delay for Logic Cell
Table 21: Logic Cells
Symbol
Parameter
Condition
Propagation delay (ns)
Fanout = 1
tPD
Combinational Delay a
a. Stated timing for worst case Propagation Delay over process variation at VCC = 2.5 V and
TA = 25 °C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the operating range.
Figure 29
0.257
tSU
Setup Time b
b. These limits are derived from a representative selection of the slowest paths through the logic cell
including typical net delays. Worst case delay values for specific paths should be determined from
timing analysis of your particular design.
Figure 30
0.22
tH
Hold Time
0
tCLK
Clock to Q Delay
Figure 31
0.255
tCWHI
Clock High Time
Figure 32
0.46
tCWLO
Clock Low Time
0.46
tSET
Set Delay
Figure 33
0.18
tRESET
Reset Delay
0.09
tSW
Set Width
0.30
tRW
Reset Width
0.30
reset
clk
d
set
q
tPD
input
output
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