© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
41
www.quicklogic.com
I/O Cell Structure
I/O Cell Structure General Description
The QuickSD device features a variety of distinct I/O pins to maximize performance,
functionality, and flexibility with bi-directional I/O pins and input-only pins. All input and I/O
pins are 2.5 V and 3.3 V tolerant and comply with the specific I/O standard selected. The
outputs swing from Vss to VCCIO (0 V to 3.3 V ± 10%). The VCCIO pins must be tied to
a 3.3 V supply to provide 3.3 V compliance.
If 3.3 V compliance is not required, then these pins must be tied to the 2.5 V supply.
Table 33
summarizes the I/O specifications that are supported.
As designs become more complex and requirements more stringent, varying I/O standards
are developing for specific applications. I/O standards for processors, memories and various
bus applications have become common place and a requirement for many systems. In
addition, I/O timing has become a greater issue with specific requirements for setup, hold,
clock to out, and switching times.
The QuickSD device has addressed these changing system requirements. The QuickSD
device includes a completely new I/O cell which consists of programmable I/Os as well as a
new cell structure consisting of three registers: input, output and output enable. The QuickSD
device offers banks of programmable I/O that addresses many of the new bus standards that
are popular today. In addition, the input register addresses the setup time, the output register
addresses clock-to-out time, and the OE register addresses the switching time from high
impedance to a given value.
Figure 51
shows the QuickSD device I/O cell.
Table 33: Supported I/O Specifications
/O Standard Reference Voltage Output Voltage
Application
LVTTL
n/a
3.3
general purpose
LVCMOS2
n/a
2.5
general purpose
PCI
n/a
3.3
PCI bus applications
GTL+
1
n/a
high speed bus - Pentium Pro
SSTL3
1.5
3.3
memory bus - Hitachi, IBM
SSTL2
1.25
2.5
memory bus - Hitachi, IBM
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