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QL82SD Device Data Sheet Rev C
Preliminary
18
SERDES Switching Characteristics - Deserializer/Receiver
a. These values include the delay resulting from application of internal compensation for data/clock skew.
Table 17: Deserializer / Receiver Switch Characteristics
CDR (10:1) Mode
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tRCP
ChX_rxclk Period
28.5
T
40.0
nS
tRDC
ChX_rxclk Duty Cycle
45
50
55
%
tDD
Deserializer Delay
Figure 23
2
× t
RCP + 1.5
2
× t
RCP + 2.5
2
× t
RCP + 3.5
nS
tRXPD
ChX_rxclk to ChX_rxd[9..0]
1.5
2.5
3.5
nS
tDSR1
Deserializer PLL Lock Time
from powered-down state
Figure 24: 25 MHz
Figure 24: 50 MHz
5
8
uS
uS
tDSR2
Deserializer PLL Lock Time from SYNCPAT
Figure : 25 MHz
Figure : 50 MHz
1
0.75
uS
uS
tDJIT
Pad_ChX_p/n Jitter
25 MHz
50 MHz
±350
±200
pS
pS
Channel Link (8:1, 7:1, 4:1) Mode
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tRCP
ChX_rxclk Period
T
nS
tRDC
ChX_rxclk Duty Cycle
45
50
55
%
tDD
Deserializer Delay
Figure 26
2
× t
RCP + 1.5
2
× t
RCP + 2.5
2
× t
RCP + 3.5
nS
tRXPD
ChX_rxclk to ChX_rxd[N-1..0]
1.5
2.5
3.5
nS
tRXDS
Pad_ChX_p/n Setup to Strobe Position
150
200
pS
tRXDH
Pad_ChX_p/n Hold to Strobe Position
150
200
pS
tSCD
Pad_ClkX_p/n to Serial Clock Delay
a
0.6
0.8
1
nS
tSCP
Serial Clock Period
T/mode
nS
tRXD[N-1]
Receiver Input Strobe Position for Bit [N-1]
[N-1]
× t
SCP + 1.1
[N-1]
× t
SCP + 2.4
nS
tDSR1
Deserializer PLL Lock Time from
powered-down state
Figure 24: 25 MHz
Figure 24: 50 MHz
5
8
uS
uS
tDJIT
Pad_ChX_p/n Jitter
25 MHz
50 MHz
±300
±150
pS
pS
Asynchronous Level Conversion (1:1) Mode
tADD
Asynchronous Deserializer Delay -
Data Channel
Figure 27
1.7
nS
tADC
Asynchronous Serializer Delay -
Channel Clock
a
0.6
0.8
1
nS
LVDS Link
Frequency
Compression
Mode
-1
Mode Dependent
LVDS Link
Frequency
Compression
Mode
-1
Mode Dependent
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