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© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
25
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Figure 36: Input Register Cell
Table 24: Input Register Cell
Symbol
Input Register Cell Only
Parameter
Propagation
Delay (ns)
tISU
Input Register Setup Time: the amount of time the synchronous
input of the flip flop must be stable before the active clock edge.
3.12
tIH
Input Register Hold Time: the amount of time the synchronous input
of the flip flop must be stable after the active clock edge.
0
tICLK
Input Register Clock to Q: the amount of time taken by the flip flop
to output after the active clock edge.
1.08
tIRST
Input Register Reset Delay: the amount of time between when the
flip flop is “reset” (low) and when Q is consequently “reset” (low).
0.99
tIESU
Input Register Clock Enable Setup Time: the amount of time
“enable” must be stable before the active clock edge.
0.37
tIEH
Input Register Clock Enable Hold Time: the amount of time “enable”
must be stable after the active clock edge.
0
PAD
E
R
Q
D
+
-
TIN, TINI
TISU
TICLK
tSID
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