28 / 60 page
www.quicklogic.com
© 2002 QuickLogic Corporation
•
•
•
•
•
•
QL82SD Device Data Sheet Rev C
Preliminary
28
RAM Cell Synchronous Write Timing
Table 27: RAM Cell Synchronous Write Timing
Figure 41: RAM Cell Synchronous Write Timing
Symbol
Parameter
Propagation
delay (ns)
tSWA
WA setup time to WCLK: the amount of time the WRITE ADDRESS
must be stable before the active edge of the WRITE CLOCK
0.675
tHWA
WA hold time to WCLK: the amount of time the WRITE ADDRESS
must be stable after the active edge of the WRITE CLOCK
0
tSWD
WD setup time to WCLK: the amount of time the WRITE DATA must
be stable before the active edge of the WRITE CLOCK
0.654
tHWD
WD hold time to WCLK: the amount of time the WRITE DATA must
be stable after the active edge of the WRITE CLOCK
0
tSWE
WE setup time to WCLK: the amount of time the WRITE ENABLE
must be stable before the active edge of the WRITE CLOCK
0.623
tHWE
WE hold time to WCLK: the amount of time the WRITE ENABLE must
be stable after the active edge of the WRITE CLOCK
0
tWCRD
WCLK to RD (WA=RA): the amount of time between the active WRITE
CLOCK edge and the time when the data is available at RD
4.38
tSWA
tSWD
tSWE
tHWA
tHWD
tHWE
tWCRD
old data
new data
WCLK
WA
WD
WE
RD
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
