LXT386LE datasheet(64/78 Pages) INTEL

64 / 78 page

LXT386 — QUAD T1/E1/J1 Transceiver

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Valid write signal pulse width

Tvwr

––

Inactive write to inactive INT delay time

Tint

––

Chip select to RDY delay time3

Tdrdy

–

Active ready Low time

Tvrdy

––

Inactive ready to tri-state delay time3

Trdyz

––

3ns

Figure 23. Non-Multiplexed Intel Mode Write Timing

Table 47. Intel Mode Write Timing Characteristics (Continued)

Parameter2

Sym

Min

Typ1

Max

Unit

Test Conditions

1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.

2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF.

3. These times don’t apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset

Operation and Host Mode sections for more information.

A4-A0

ALE

D7-D0

RDY

Tristate

ADDRESS

INT

tSCSW

tVWR

tDRDY

tVRDY

tHCSW

WRITE DATA

tSDW

tHDW

tINT

tDRDY

tRDYZ

(pulled High)

tSAW

tHAW

LXT386LE Datasheet(PDF) 64 Page - Intel Corporation

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