LXT386LE datasheet(42/78 Pages) INTEL

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LXT386 — QUAD T1/E1/J1 Transceiver

Datasheet

Table 22. Automatic TAOS Select Register, ATS (0EH)

Bit1

Name

Function

3-0

ATS3-ATS0

Setting a bit to “1” enables automatic TAOS generation whenever a LOS condition is

detected in the respective transceiver.

7-4

Write “0” to these positions for normal operation.

1. On power-on reset the register is set to “0”.

2. This feature is not available in data recovery and line driver mode (MCLK= High and TCLK = High)

Table 23. Global Control Register, GCR (0FH)

Bit1

Name

Function

JASEL0

These bits determine the jitter attenuator position:

JASEL1

2JACF

This bit determines the jitter attenuator low limit 3dB corner frequency. Refer to the Jitter

Attenuator specifications for details (Table 41 on page 58).

3FIFO64

This bit determines the jitter attenuator FIFO depth:

0 = 32 bit

1 = 64 bit

4CODEN

This bit selects the zero suppression code for unipolar operation mode:

0 = B8ZS/HDB3 (T1/E1 respectively)

1 = AMI

CDIS

This bit controls enables/disables the short circuit protection feature:

0 = enabled

1 = disabled

RAISEN

This bit controls automatic AIS insertion in the receive path when LOS occurs:

0 = Receive AIS insertion disabled on LOS

1 = RPOS/RNEG = AIS on LOS

Note: this feature is not available in data recovery mode (MCLK=High). Disable AIS

interrupts when changing this bit value to prevent inadvertent interrupts.

Reserved.

1. On power-on reset the register is set to “0”.

JASEL0

JASEL1

JA Position

Transmit Path

Receive Path

Disabled

LXT386LE Datasheet(PDF) 42 Page - Intel Corporation

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