LXT386LE datasheet(37/78 Pages) INTEL

37 / 78 page

QUAD T1/E1/J1 Transceiver — LXT386

Datasheet

occurs, the INT pin is asserted Low. The output stage of the INT pin consists only of a pull-down

device; an external pull-up resistor of approximately 10k ohm is required to support wired-OR

operation.

3.13.2

Interrupt Clear

When an interrupt occurs, the interrupt service routine (ISR) should read the interrupt status

registers (08H, 09H and 15H) to identify the interrupt source. Reading the Interrupt Status register

clears the “sticky” bit set by the interrupt. Automatically clearing the register prepares it for the

next interrupt.

The ISR should then read the corresponding status monitor register to obtain the current status of

the device. Note that there are three status monitor registers: the LOS (04H), the DFM (05H) and

the AIS (013H). Reading either status monitors register will clear its corresponding interrupts on

the rising edge of the read or data strobe. When all pending interrupts are cleared, the INT pin goes

High.

3.14

Serial Host Mode

The LXT386 operates in Serial Host Mode when the MODE pin is tied to VCC

÷2. Figure 14 shows

the SIO data structure. The registers are accessible through a 16 bit word: an 8bit Command/

Address byte (bits R/W and A1-A7) and a subsequent 8bit data byte (bits D0-7). Bit R/W

determines whether a read or a write operation occurs. Bits A5-0 in the Command/Address byte

address specific registers (the address decoder ignores bits A7-6). The data byte depends on both

the value of bit R/W and the address of the register as set in the Command/Address byte.

Figure 14. Serial Host Mode Timing

SCLK

ADDRESS/COMMAND BYTE

INPUT DATA BYTE

R/W

SDI

SDO - REMAINS HIGH Z

R/W = 1: Read from the LXT386

X = Don’t care

SDO IS DRIVEN IF R/W = 1

R/W = 0: Write to the LXT386

LXT386LE Datasheet(PDF) 37 Page - Intel Corporation