LXT386LE datasheet(65/78 Pages) INTEL

65 / 78 page

QUAD T1/E1/J1 Transceiver — LXT386

Datasheet

Figure 24. Multiplexed Intel Mode Write Timing

Table 48. Motorola Bus Read Timing Characteristics

Parameter2

Sym

Min

Typ1

Max

Unit

Test Conditions

Address setup time to address or data strobe

Tsar

––

Address hold time from address or data strobe

Thar

––

Valid address strobe pulse width

Tvas

––

R/W setup time to active data strobe

Tsrw

––

R/W hold time from inactive data strobe

Thrw

––

Chip select setup time to active data strobe

Tscs

––

Chip select hold time from inactive data strobe

Thcs

––

Address strobe active to data strobe active delay

Tasds

––

Delay time from active data strobe to valid data

Tpds

–

Delay time from inactive data strobe to data High Z

Tdz

–

Valid data strobe pulse width

Tvds

––

Inactive data strobe to inactive INT delay time

Tint

––

Data strobe inactive to address strobe inactive delay

Tdsas

––

DS asserted to ACK asserted delay

Tdackp

––

DS deasserted to ACK deasserted delay

Tdack

––

Active ACK to valid data delay

Tpack

––

0ns

1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.

2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF.

ALE

AD7-AD0

RDY

Tristate

ADDRESS

INT

tVL

tSLW

tSCSW

tHALW

tSALW

tDRDY

tVRDY

tVWR

tHCSW

tSDW

WRITE DATA

tHDW

tINT

tDRDY

tDRDYZ

LXT386LE Datasheet(PDF) 65 Page - Intel Corporation

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