LXT386LE datasheet(7/78 Pages) INTEL

7 / 78 page

QUAD T1/E1/J1 Transceiver — LXT386

Datasheet

1.0

Features

• Single rail 3.3V supply with 5V tolerant inputs

• Low power consumption of 150mW per channel (typical)

• Superior crystal-less jitter attenuator

— Meets ETSI CTR12/13, ITU G.736, G.742, G.823 and AT&T Pub 62411 specifications

— Optimized for SONET/SDH applications, meets ITU G.783 mapping jitter specification

— Constant throughput delay jitter attenuator

• Hitless Protection Switching (HPS) for 1 to 1 protection without relays

• HDB3, B8ZS, or AMI line encoder/decoder

• Provides protected monitoring points per ITU G.772

• Analog/digital and remote loopback testing functions

• LOS per ITU G.775, ETS 300 233 and T1.231

• 8 bit parallel or 4 wire serial control interface

• Hardware and Software control modes

• JTAG Boundary Scan test port per IEEE 1149.1

• 160 PBGA and 100 pin LQFP packages

Figure 1. LXT386 Block Diagram

HARDWARE / SOFTWARE CONTROL

(JTAG INTERFACE)

DATA SLICER

LINE DRIVER

DATA

CLOCK

PULSE

MCLK

LOS

CLOCK

RECOVERY

PULSE

SHAPER

TPOS

TCLK

TNEG

RPOS

RCLK

RNEG

B8ZS / HDB3

DECODER

B8ZS / HDB3

ENCODER

JITTER

ATTENUATOR

RX OR TX

PATH

JITTER

ATTENUATOR

RX OR TX

PATH

MODE

CLKE

LOOP 0..3

RTIP

RRING

TTIP

TRING

JTAG

SERIAL/

PARALLEL

PORT

JASEL

LXT386LE Datasheet(PDF) 7 Page - Intel Corporation

LXT386LE Datasheet(HTML) 7 Page - Intel Corporation

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