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LXT386LE Datasheet(PDF) 60 Page - Intel Corporation

Part # LXT386LE
Description  QUAD T1/E1/J1 Transceiver
PDF  78 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

LXT386LE Datasheet(HTML) 60 Page - Intel Corporation

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LXT386 — QUAD T1/E1/J1 Transceiver
60
Datasheet
Table 44. Receive Timing Characteristics
Parameter
Sym
Min
Typ
Max
Unit
Test Condition
Clock recovery capture range
E1
––
±80
–
ppm
Relative to
nominal frequency
MCLK = ±100
ppm
T1
––
±180
–
ppm
Receive clock duty cycle 1
Rckd
40
50
60
%
Receive clock pulse width 1
E1
Tpw
447
488
529
ns
T1
Tpw
583
648
713
ns
Receive clock pulse width Low time
E1
Tpwl
203
244
285
ns
T1
Tpwl
259
324
389
ns
Receive clock pulse width High time
E1
Tpwh
203
244
285
ns
T1
Tpwh
259
324
389
ns
Rise/fall time 4
Tr
20
––
ns
@ CL=15 pF
RPOS/RNEG pulse width (MCLK=H) 2
E1
Tpwdl
200
244
300
ns
T1
Tpwdl
250
324
400
ns
RPOS/RNEG to RCLK rising setup time
E1
Tsur
200
244
–
ns
T1
200
324
–
ns
RCLK Rising to RPOS/RNEG hold time
E1
Thr
200
244
–
ns
T1
200
324
–
ns
Delay time between RPOS/RNEG and RCLK
––
–
5
ns
MCLK = H 3
1. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK
duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823).
2. Clock recovery is disabled in this mode.
3. If MCLK = H the receive PLLs are replaced by a simple EXOR circuit.
4. For all digital outputs.
Figure 19. Receive Clock Timing Diagram
CLKE = 0
RPOS
RNEG
CLKE = 1
RPOS
RNEG
RCLK
tPW
tPWH
tSUR
tPWL
tHR
tHR
tSUR



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