LXT386LE datasheet(59/78 Pages) INTEL

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QUAD T1/E1/J1 Transceiver — LXT386

Datasheet

Table 42. Analog Test Port Characteristics

Parameter

Sym

Min

Typ

Max

Unit

Test Condition

3 dB bandwidth

At13db

MHz

Input voltage range

At1iv

VCC

Output voltage range

At2ov

VCC

Table 43. Transmit Timing Characteristics

Parameter

Sym

Min

Typ

Max

Unit

Test Condition

Master clock frequency

MCLK

–

2.048

–

MHz

MCLK

–

1.544

–

MHz

Master clock tolerance

–

-100

–

100

ppm

Master clock duty cycle

–

Output pulse width

219

244

269

291

324

356

Transmit clock frequency

Tclke1

2.048

MHz

Tclkt1

1.544

MHz

Transmit clock tolerance

Tclkt

-50

–

+50

ppm

Transmit clock burst rate

Tclkb

–

MHz

Gapped transmit clock

Transmit clock duty cycle

Tdc

–

NRZ mode

E1 TPOS/TNEG pulse width (RZ mode)

Tmpwe1

236

–

252

RZ mode (TCLK = H for

>16 clock cycles)

TPOS/TNEG to TCLK setup time

Tsut

TCLK to TPOS/TNEG hold time

Tht

Delay time OE Low to driver High Z

Toez

µs

Delay time TCLK Low to driver High Z

Ttz

µs

Figure 18. Transmit Clock Timing Diagram

TPOS

TNEG

TCLK

tHT

tSUT

LXT386LE Datasheet(PDF) 59 Page - Intel Corporation

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