LXT386LE datasheet(18/78 Pages) INTEL

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LXT386 — QUAD T1/E1/J1 Transceiver

Datasheet

J14

DS/

WR/

SDI/

LEN0

Data Strobe (Motorola Mode).

Write Enable (Intel mode).

Serial Data Input (Serial Mode).

Line Length Equalizer (Hardware Mode).

Host Mode

This pin acts as data strobe in Motorola mode and as Write Enable in Intel

mode. In serial mode this pin is used as Serial Data Input.

Hardware Mode

This pin determines the shape and amplitude of the transmit pulse. Refer

to Table 2.

J13

R / W/

RD/

LEN1

Read/Write (Motorola Mode).

Read Enable (Intel mode).

Line Length Equalizer (Hardware Mode).

Host Mode

This pin functions as the read/write signal in Motorola mode and as the

Read Enable in Intel mode.

Hardware Mode

This pin determines the shape and amplitude of the transmit pulse. Refer

to Table 2.

J12

ALE/

SCLK/

AS/

LEN2

Address Latch Enable (Host Mode).

Shift Clock (Serial Mode).

Address Strobe (Motorola Mode).

Line Length Equalizer (Hardware Mode).

Host Mode

The address on the multiplexed address/data bus is clocked into the

device with the falling edge of ALE.

In serial Host mode this pin acts as serial shift clock.

In Motorola mode this pin acts a an active Low address strobe.

Hardware Mode

This pin determines the shape and amplitude of the transmit pulse. Refer

to Table 2.

Table 1.

Pin Assignments and Signal Descriptions (Continued)

Ball #

PBGA

Pin #

LQFP

Symbol

I/O1

Description

1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;

N.C.: Not Connected.

2. N/C means “Not Connected”

LXT386LE Datasheet(PDF) 18 Page - Intel Corporation

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